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mb95650l series new 8fx 8-bit microcontrollers cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-04696 rev. *a revised april 12, 2016 the mb95650l series is a series of general-purpose, single-chip mi crocontrollers. in addition to a compact instruction set, the microcontrollers of this series cont ain a variety of peripheral functions. features f 2 mc-8fx cpu core instruction set opti mized for controllers multiplication and division instructions 16-bit arithmetic operations bit test branch instructions bit manipulation instructions, etc. clock selectable main clock source ? main oscillation clock (up to 16.25 mhz, maximum machine clock frequency: 8.125 mhz) ? external clock (up to 32.5 mhz, maximum machine clock frequency: 16.25 mhz) ? main cr clock (4 mhz ? 2%) ? main cr pll clock ? the main cr pll clock frequency becomes 8 mhz ? 2% when the pll multiplication rate is 2. ? the main cr pll clock frequency becomes 10 mhz ? 2% when the pll multiplic ation rate is 2.5. ? the main cr pll clock frequency becomes 12 mhz ? 2% when the pll multiplication rate is 3. ? the main cr pll clock frequency becomes 16 mhz ? 2% when the pll multiplication rate is 4. ? main pll clock (maximum machine clock frequency: 16 mhz) selectable subclock source ? suboscillation clock (32.768 khz) ? external clock (32.768 khz) ? sub-cr clock (typ: 100 khz, min: 50 khz, max: 150 khz) timer 8/16-bit composite timer ? 2 channels time-base timer ? 1 channel watch prescaler ? 1 channel uart/sio ? 1 channel (the channel can be used either as a uart/sio channel or as an i 2 c bus interface channel.) the function of this channel can be switched between uart/sio and i 2 c bus interface. full duplex double buffer capable of clock asynchronous (uart) serial data transfer and clock synchronous (sio) serial data transfer i 2 c bus interface ? 2 channels (one of the two channels can be used either as an i 2 c bus interface channel or as a uart/sio channel.) supports standard-mode and fast-mode (400 khz). built-in wake-up function lin-uart full duplex double buffer capable of clock asynchronous serial data transfer and clock synchronous serial data transfer external interrupt ? 6 channels interrupt by edge detection (rising edge, falling edge, and both edges can be selected) can be used to wake up the device from different low power consumption (standby) modes 8/12-bit a/d converter ? 6 channels 8-bit or 12-bit resolution can be selected. low power consumption (standby) modes there are four standby modes as follows: stop mode sleep mode watch mode time-base timer mode i/o port mb95f652e/f653e/f654e/f656e (number of i/o ports: 21) ? general-purpose i/o ports (cmos i/o) : 17 ? general-purpose i/o port s (n-ch open drain) : 4 mb95f652l/f653l/f654l/f656l (number of i/o ports: 20) ? general-purpose i/o ports (cmos i/o) : 17 ? general-purpose i/o port s (n-ch open drain) : 3 on-chip debug 1-wire serial control serial writing supported (asynchronous mode) hardware/software watchdog timer built-in hardware watchdog timer built-in software watchdog timer
document number: 002-04696 rev. *a page 2 of 105 mb95650l series power-on reset a power-on reset is generated when the power is switched on. low-voltage detection reset circuit and low-voltage detection interrupt circuit (only available on mb95f652e/f653e/f654e/f656e) built-in low-voltage detection function clock supervisor counter built-in clock supervisor counter dual operation flash memory the program/erase operation and the read operation can be executed in different banks (upper bank/lower bank) simultaneously. flash memory security function protects the content of the flash memory.
document number: 002-04696 rev. *a page 3 of 105 mb95650l series contents product line-up ................................................................ 4 packages and corresponding products ........................ 6 differences among products and notes on product selection ............................................. 7 pin assignment ................................................................ 8 pin functions .................................................................... 9 i/o circuit type ............................................................... 12 handling precautions ..................................................... 15 precautions for product design ................................. 15 precautions for package mount ing ............ ........... .... 16 precautions for use environment .............................. 17 notes on device handling ............................................. 18 pin connection ............................................................... 19 block diagram ................................................................ 20 cpu core ......................................................................... 21 memory space ................................................................ 22 areas for specific applications .................................... 24 i/o map ............................................................................. 25 i/o ports ........................................................................... 29 port 0 ......................................................................... 30 port 1 ......................................................................... 36 port 6 ......................................................................... 42 port f ......................................................................... 46 port g ........................................................................ 50 interrupt source table ................................................... 53 pin states in each mode ................................................ 54 electrical characteristics ............................................... 56 absolute maximum ratings ... .................................... 56 recommended operating conditions ....................... 58 dc characteristics .................................................... 59 ac characteristics ..................................................... 62 a/d converter ............................................................ 86 flash memory program/erase characteristics .......... 90 sample characteristics .................................................. 91 mask options .................................................................. 98 ordering information ...................................................... 99 package dimension ...................................................... 100 major changes .............................................................. 103 document history ......................................................... 104
document number: 002-04696 rev. *a page 4 of 105 mb95650l series 1. product line-up (continued) part number parameter mb95f652e mb95f653e mb95f654e mb95f656e mb95f652l mb95f653l mb95f654l mb95f656l type flash memory product clock supervisor counter it supervises the main clock oscilla tion and the subclock oscillation. flash memory capacity 8 kbyte 12 kbyte 20 kbyte 36 kbyte 8 kbyte 12 kbyte 20 kbyte 36 kbyte ram capacity 256 bytes 512 bytes 1024 bytes 1024 bytes 256 bytes 512 bytes 1024 bytes 1024 bytes power-on reset yes low-voltage detection reset yes no reset input selected through software with dedicated reset input cpu functions ? number of basic instructions : 136 ? instruction bit length : 8 bits ? instruction length : 1 to 3 bytes ? data bit length : 1, 8 and 16 bits ? minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 mhz) ? interrupt processing time : 0.6 s (machine clock frequency = 16.25 mhz) general-purpose i/o ? i/o port : 21 ? cmos i/o : 17 ? n-ch open drain : 4 ? i/o port : 20 ?cmos i/o :17 ? n-ch open drain : 3 time-base timer interval time: 0.256 ms to 8.3 s (external clock frequency = 4 mhz) hardware/software watchdog timer ? reset generation cycle main oscillation clock at 10 mhz: 105 ms (min) ? the sub-cr clock can be used as the source clock of the software watchdog timer. wild register it can be used to replace 3 bytes of data. lin-uart ? a wide range of communication speed can be selected by a dedicated reload timer. ? it has a full duplex double buffer. ? both clock synchronous serial data transfer and clock asynchronous serial data transfer are enabled. ? the lin function can be used as a lin master or a lin slave. 8/12-bit a/d converter 6 channels 8-bit or 12-bit resolution can be selected. 8/16-bit composite timer 2 channels ? the timer can be configured as an ?8-bit timer 2 channels? or a ?16-bit timer 1 channel?. ? it has the following functions: interval timer function , pwc function, pwm function and input capture function. ? count clock: it can be selected from internal clocks (seven types) and external clocks. ? it can output square wave. external interrupt 6 channels ? interrupt by edge detection (the rising edge, falling edge, and both edges can be selected.) ? it can be used to wake up the device from different standby modes. on-chip debug ? 1-wire serial control ? it supports serial writing (asynchronous mode).
document number: 002-04696 rev. *a page 5 of 105 mb95650l series (continued) part number parameter mb95f652e mb95f653e mb95f654e mb95f656e mb95f652l mb95f653l mb95f654l mb95f656l uart/sio 1 channel (the channel can be used eit her as a uart/sio channel or as an i 2 c bus interface channel.) ? data transfer with uart/sio is enabled. ? it has a full duplex double buffer, variable data length (5/6/7/8 bits), an internal baud rate generator and an error detection function. ? it uses the nrz type transfer format. ? lsb-first data transfer and msb-first data transfer are available to use. ? both clock asynchronous (uart) serial data transfer and clock synchronous (sio) serial data transfer are enabled. i 2 c bus interface 2 channels (one of the two channels can be used either as an i 2 c bus interface channel or as a uart/sio channel.) ? master/slave transmission and reception ? it has the following functions: bus error function, arbitr ation function, transmission direction detection function, wake-up function, and functions of generating and detecting repeated start conditions. watch prescaler eight different time intervals can be selected. flash memory ? it supports automatic programming (embedded algorit hm), and program/erase/erase-suspend/erase-resume commands. ? it has a flag indicating the completion of the operation of embedded algorithm. ? flash security feature for protec ting the content of the flash memory standby mode there are four standby modes as follows: ? stop mode ? sleep mode ? watch mode ? time-base timer mode package FPT-24P-M10 fpt-24p-m34 lcc-32p-m19 number of program/er ase cycles 1000 10000 100000 data retention time 20 years 10 years 5 years
document number: 002-04696 rev. *a page 6 of 105 mb95650l series 2. packages and corresponding products ? : available part number package mb95f652e mb95f653e mb95f654e mb95f656e mb95f652l mb95f653l mb95f654l mb95f656l FPT-24P-M10 ???????? fpt-24p-m34 ???????? lcc-32p-m19 ????????
document number: 002-04696 rev. *a page 7 of 105 mb95650l series 3. differences among products and notes on product selection current consumption when using the on-chip debug function, take account of the current consumption of flash memory program/erase. for details of current consumption, s ee ?18. electrical characteristics?. package for details of information on each package, see ?2. pack ages and corresponding products? and ?22. package dimension?. operating voltage the operating voltage varies, depending on whether the on-chip debug function is used or not. for details of operating voltage, see ?18. electrical characteristics?. on-chip debug function the on-chip debug function requires that v cc , v ss and one serial wire be connected to an evaluation tool. for details of the connection method, refer to ?chapter 20 example of serial programming connection? in ?new 8fx mb95650l series hardware manual?.
document number: 002-04696 rev. *a page 8 of 105 mb95650l series 4. pin assignment p12/dbg/ec0 p07/int07/to10 p06/int06/to01 p05/int05/an05/to00 p04/int04/an04/sin/ec0 p03/int03/an03/sot p02/int02/an02/sck p01/an01 p00/an00 p64/ec1 p14/sda0 p15/scl0 pf2/rst pf1/x1 pf0/x0 vss pg2/x1a pg1/x0a vcc c p17/scl1/ui0 p16/sda1/uo0 p62/to10/uck0 p63/to11 (top view) tssop24 FPT-24P-M10 sop24 fpt-24p-m34 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 pf0/x0 pf1/x1 nc nc nc nc p07/int07/to10 p12/dbg/ec0 p06/int06/to01 p05/int05/an05/to00 p04/int04/an04/sin/ec0 p03/int03/an03/sot vss pg2/x1a pg1/x0a vcc c p17/scl1/ui0 p16/sda1/uo0 (top view) qfn32 lcc-32p-m19 32 31 30 29 28 27 26 25 24 23 22 21 p02/int02/an02/sck p01/an01 p00/an00 p64/ec1 20 19 18 17 1 2 3 4 5 6 7 8 p63/to11 p62/to10/uck0 nc nc 9 10 11 12 nc nc p14/sda0 13 14 15 p15/scl0 16 pf2/rst
document number: 002-04696 rev. *a page 9 of 105 mb95650l series 5. pin functions (continued) pin no. pin name i/o circuit type* 4 function i/o type sop24* 1 , tssop24* 2 qfn32* 3 input output od* 5 pu* 6 132 pf0 b general-purpose i/o port hysteresis cmos ? ? x0 main clock input oscillation pin 231 pf1 b general-purpose i/o port hysteresis cmos ? ? x1 main clock i/o oscillation pin 31v ss ? power supply pin (gnd) ? ? ? ? 42 pg2 c general-purpose i/o port hysteresis cmos ? ? x1a subclock i/o oscillation pin 53 pg1 c general-purpose i/o port hysteresis cmos ? ? x0a subclock input oscillation pin 64v cc ? power supply pin ? ? ? ? 7 5 c ? decoupling capacitor connection pin ? ? ? ? 86 pf2 a general-purpose i/o port hysteresis cmos ? ? rst reset pin dedicated reset pin on mb95f652l/f653l/f654l/f656l 97 p17 j general-purpose i/o port cmos cmos ?/ ? * 7 ? scl1 i 2 c bus interface ch. 1 clock i/o pin ui0 uart/sio ch. 0 data input pin 10 8 p16 j general-purpose i/o port cmos cmos ?/ ? * 7 ? sda1 i 2 c bus interface ch. 1 data i/o pin uo0 uart/sio ch. 0 data output pin 11 10 p62 d general-purpose i/o port high-current pin hysteresis cmos ? ? to10 8/16-bit composite timer ch. 1 output pin uck0 uart/sio ch. 0 clock i/o pin 12 9 p63 d general-purpose i/o port high-current output hysteresis cmos ? ? to11 8/16-bit composite timer ch. 1 output pin 13 16 p15 i general-purpose i/o port cmos cmos ? ? scl0 i 2 c bus interface ch. 0 clock i/o pin 14 15 p14 i general-purpose i/o port cmos cmos ? ? sda0 i 2 c bus interface ch. 0 data i/o pin 15 17 p64 d general-purpose i/o port hysteresis cmos ? ? ec1 8/16-bit composite timer ch. 1 clock input pin
document number: 002-04696 rev. *a page 10 of 105 mb95650l series (continued) pin no. pin name i/o circuit type* 4 function i/o type sop24* 1 , tssop24* 2 qfn32* 3 input output od* 5 pu* 6 16 18 p00 e general-purpose i/o port hysteresis/ analog cmos ? ? an00 8/12-bit a/d converter analog input pin 17 18 p01 e general-purpose i/o port hysteresis/ analog cmos ? ? an01 8/12-bit a/d converter analog input pin 18 20 p02 e general-purpose i/o port hysteresis/ analog cmos ? ? int02 external interrupt input pin an02 8/12-bit a/d converter analog input pin sck lin-uart clock i/o pin 19 21 p03 e general-purpose i/o port hysteresis/ analog cmos ? ? int03 external interrupt input pin an03 8/12-bit a/d converter analog input pin sot lin-uart data output pin 20 22 p04 f general-purpose i/o port cmos/ analog cmos ? ? int04 external interrupt input pin an04 8/12-bit a/d converter analog input pin sin lin-uart data input pin ec0 8/16-bit composite timer ch. 0 clock input pin 21 23 p05 k general-purpose i/o port high-current pin hysteresis/ analog cmos ? ? int05 external interrupt input pin an05 8/12-bit a/d converter analog input pin to00 8/16-bit composite timer ch. 0 output pin 22 24 p06 d general-purpose i/o port high-current pin hysteresis cmos ? ? int06 external interrupt input pin to01 8/16-bit composite timer ch. 0 output pin 23 26 p07 k general-purpose i/o port high-current pin hysteresis cmos ? ? int07 external interrupt input pin to10 8/16-bit composite timer ch. 1 output pin
document number: 002-04696 rev. *a page 11 of 105 mb95650l series (continued) ? : available *1: fpt-24p-m34 *2: FPT-24P-M10 *3: lcc-32p-m19 *4: for the i/o circuit types, see ?6. i/o circuit type?. *5: n-ch open drain *6: pull-up *7: in i 2 c mode, the pin becomes an n-ch open drain pin. pin no. pin name i/o circuit type* 4 function i/o type sop24* 1 , tssop24* 2 qfn32* 3 input output od* 5 pu* 6 24 25 p12 h general-purpose i/o port hysteresis cmos ? ? dbg dbg input pin ec0 8/16-bit composite time r ch. 0 clock input pin ? 11 nc ? it is an internally connected pin. always leave it unconnected. ???? 12 13 14 27 28 29 30
document number: 002-04696 rev. *a page 12 of 105 mb95650l series 6. i/o circuit type (continued) type circuit remarks a ? n-ch open drain output ? hysteresis input ? reset output b ? oscillation circuit ? high-speed side feedback resistance: approx. 1 m ? ? cmos output ? hysteresis input c ? oscillation circuit ? low-speed side feedback resistance: approx. 5 m ? ? cmos output ? hysteresis input ? pull-up control n-ch reset output / digital output reset input / hysteresis input standby control / port select clock input port select digital output digital output standby control hysteresis input digital output digital output standby control hysteresis input port select x1 x0 n-ch p-ch n-ch p-ch clock input x1a x0a standby control / port select n-ch p-ch port select digital output digital output standby control hysteresis input n-ch digital output digital output digital output standby control hysteresis input p-ch r pull-up control port select p-ch r pull-up control
document number: 002-04696 rev. *a page 13 of 105 mb95650l series (continued) type circuit remarks d ? cmos output ? hysteresis input ? pull-up control ? high current output e ? cmos output ? hysteresis input ? pull-up control ? analog input f ? cmos output ? cmos input ? pull-up control ? analog input h ? n-ch open drain output ? hysteresis input i ? n-ch open drain output ? cmos input n-ch p-ch p-ch r pull-up control digital output digital output standby control hysteresis input n-ch p-ch p-ch r pull-up control digital output digital output analog input a/d control standby control hysteresis input n-ch p-ch p-ch r pull-up control digital output digital output analog input a/d control standby control cmos input n-ch standby control hysteresis input digital output n-ch digital output standby control cmos input
document number: 002-04696 rev. *a page 14 of 105 mb95650l series (continued) type circuit remarks j ? cmos output ? cmos input ? n-ch open drain output in i 2 c mode k ? cmos output ? hysteresis input ? pull-up control ? analog input ? high current output n-ch p-ch i 2 c mode control digital output digital output standby control cmos input n-ch p-ch p-ch r pull-up control digital output digital output analog input a/d control standby control hysteresis input
document number: 002-04696 rev. *a page 15 of 105 mb95650l series 7. handling precautions any semiconductor devices have inherently a certain rate of fa ilure. the possibility of failure is greatly affected by the cond itions in which they are used (circuit conditions, envi ronmental conditions, etc.). this page de scribes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your cypress semiconductor devices. 7.1 precautions for product design this section describes precautions when designing electronic equipment using semiconductor devices. absolute maximum ratings semiconductor devices can be pe rmanently damaged by application of stress (voltage, current, temp erature, etc.) in excess of ce rtain established limits, called absolute maximum ratings. do not exceed these ratings. recommended operating conditions recommended operating conditions are normal operating ranges for the semiconductor dev ice. all the device's electrical characte r- istics are warranted when operated within these ranges. always use semiconductor devices within the recommended operati ng conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not re presented on the data sheet. users consid ering application outside the listed conditions are advised to contact their sales representative beforehand. processing and protection of pins these precautions must be followed when handling the pins whic h connect semiconductor devices to power supply and input/output functions. 1. preventing over-voltage and over-current conditions exposure to voltage or current levels in excess of maximum ratings at any pin is lik ely to cause deterior ation within the devic e, and in extreme cases leads to permanent damage of the device. try to prevent such overvoltage or over-current conditions at the design stage. 2. protection of output pins shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. such conditions if present for extended periods of time can damage the device. therefore, avoid this type of connection. 3. handling of unused input pins unconnected input pins with very high impedanc e levels can adversely affect stability of operation. such pins should be connect ed through an appropriate resistance to a power supply pin or ground pin. latch-up semiconductor devices are constructed by t he formation of p-type and n-type areas on a substrate. when subj ected to abnormally high voltages, internal parasitic pnpn junctions (called thyristo r structures) may be formed, causing large current levels in e xcess of several hundred ma to flow continuously at the power supply pin. this condition is called latch-up. caution: the occurrence of latch-up not only causes loss of relia bility in the semiconductor device, but can cause injury or da mage from high heat, smoke or fl ame. to prevent this from happening, do the following: 1. be sure that voltages applied to pins do not exceed the absolut e maximum ratings. this should include attention to abnormal n oise, surge levels, etc. 2. be sure that abnormal current flows do not occur during the power-on sequence. observance of safety regulations and standards most countries in the world have established standards and regula tions regarding safety, protection from electromagnetic interf erence, etc. customers are requested to observe applicable re gulations and standards in the design of products. fail-safe design any semiconductor devices have inherently a certain rate of fail ure. you must protect against in jury, damage or loss from such failures by incorporating safety design measures in to your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.
document number: 002-04696 rev. *a page 16 of 105 mb95650l series precautions related to usage of devices cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communicatio ns, and measurement equipment, pers onal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage , or where extremely high levels of reliability are demanded (suc h as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices fo r life support, e tc.) are requested to consult with sales representatives before such use. the company will not be responsible for damages arising from s uch use without prior approval. 7.2 precautions for package mounting package mounting may be either lead insertion type or surface mo unt type. in either case, for heat resistance during soldering, you should only mount under cypress?s recommended conditions. for det ailed information about mount conditions, contact your sales representative. lead insertion type mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. direct mounting onto boards normally involves processes for inse rting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. in th is case, the soldering process usually causes leads to be sub jected to thermal stress in excess of the absolute ratings for storage temperature. mounting processes should conform to cypress recommended mounting conditions. if socket mounting is used, differences in su rface treatment of the socket contacts and ic lead surfaces can lead to contact deterioration after long periods. for this reason it is recommended that the surface treatment of socket contacts and ic leads be verified before mounting. surface mount type surface mount packaging has longer and thinner leads than lead-i nsertion packaging, and therefore leads are more easily deforme d or bent. the use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connecti ons caused by deformed pins, or shorting due to solder bridges. you must use appropriate mounting techniques. cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. users are advised to m ount packages in accordance with cypress ranking of recommended conditions. lead-free packaging caution: when ball grid array (bga) packages with sn-ag-cu balls are mounted using sn-pb eutectic soldering, junction strength may be reduced under some conditions of use. storage of semiconductor devices because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorptio n of moisture. during mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. to prevent, do the following: 1. avoid exposure to rapid temperature change s, which cause moisture to condense inside the product. store products in locations where temperature c hanges are slight. 2. use dry boxes for product storage. products should be stored be low 70% relative humidity, and at temperatures between 5c and 30c. when you open dry package that recommends humidity 40% to 70% relative humidity. 3. when necessary, cypress packages semiconductor devices in high ly moisture-resistant aluminum laminate bags, with a silica gel desiccant. devices should be sealed in their aluminum laminate bags for storage. 4. avoid storing packages where they are expos ed to corrosive gases or high levels of dust. baking packages that have absorbed moisture may be de-moisturized by baking (heat drying). follow the cypress recommended conditions for baking. condition: 125c/24 h
document number: 002-04696 rev. *a page 17 of 105 mb95650l series static electricity because semiconductor devices are particularly susceptible to dama ge by static electricity, you must take the following precaut ions: 1. maintain relative humidity in the working environment between 40% and 70%. use of an apparatus for ion generation may be needed to remove electricity. 2. electrically ground all conveyors, solder vess els, soldering irons and peripheral equipment. 3. eliminate static body electricity by th e use of rings or bracelets connected to ground through high resistance (on the level of 1 m ? ). wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. 4. ground all fixtures and instruments, or protect with anti-static measures. 5. avoid the use of styrofoam or other highly static-prone material s for storage of completed board assemblies. 7.3 precautions for use environment reliability of semiconductor devices depends on ambien t temperature and other conditions as described above. for reliable performance, do the following: 1. humidity prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. if high humidity levels are anticipated, consider anti-humidity processing. 2. discharge of static electricity when high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. in such cases, use anti-static measures or processing to prevent discharges. 3. corrosive gases, dust, or oil exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. i f you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. radiation, including cosmic radiation most devices are not designed for environmen ts involving exposure to radiation or cosm ic radiation. users should provide shield ing as appropriate. 5. smoke, flame caution: plastic molded devices are flamm able, and therefore should not be used near combustible substances. if devices begin to smoke or burn, there is danger of the release of toxic gases. customers considering the use of cypress products in othe r special environmental conditions should consult with sales representatives.
document number: 002-04696 rev. *a page 18 of 105 mb95650l series 8. notes on device handling preventing latch-ups when using the device, ensure that the voltage applied does not exceed the maximum voltage rating. in a cmos ic, if a voltage higher than v cc or a voltage lower than v ss is applied to an input/output pin that is neither a medium-withstand voltage pin nor a high-withstand voltage pin, or if a voltage out of the rating range of power supply voltage mentioned in ?18.1 absolute maximum ratings? of ?18. el ectrical characteristics? is applied to the v cc pin or the v ss pin, a latch-up may occur. when a latch-up occurs, power supply current increases significantly, which may cause a component to be thermally destroyed. stabilizing supply voltage supply voltage must be stabilized. a malfunction may occur when power supply voltage fluctuates ra pidly even though the fluctuation is within the guaranteed opera ting range of the v cc power supply voltage. as a rule of voltage stabilization, suppress volt age fluctuation so that the fluctuation in v cc ripple (p-p value) at the commercial frequency (50 hz/60 hz) does not exceed 10% of the standard v cc value, and the transient fluctuat ion rate does not exceed 0.1 v/ms at a momentary fluctuation such as switching the power supply. notes on using the external clock when an external clock is used, oscillation stabilization wait time is required for power-on re set, wake-up from subclock mode or stop mode.
document number: 002-04696 rev. *a page 19 of 105 mb95650l series 9. pin connection treatment of unused pins if an unused input pin is left unconnected, a component may be permanently damaged due to malfunctions or latch-ups. always pul l up or pull down an unused input pin through a resistor of at least 2 k ? . set an unused input/output pin to the output state and leave it unconnected, or set it to the input stat e and treat it the same as an unused input pin. if there is an unused output pin, le ave it unconnected. power supply pins to reduce unnecessary electro-magnetic emissi on, prevent malfunctions of strobe signals due to an increase in the ground level, and conform to the total output current standard, always connect the v cc pin and the v ss pin to the power supply and ground outside the device. in addition, connect the current supply source to the v cc pin and the v ss pin with low impedance. it is also advisable to connect a ceramic capacitor of approximately 1.0 f as a bypass capacitor between the v cc pin and the v ss pin at a location close to this device. dbg pin connect the dbg pin to an external pull-up resistor of 2 k ? or above. after power-on, ensure that the dbg pin does not st ay at ?l? level until the reset output is released. the dbg pin becomes a communication pin in debug mode. since the actual pull-up resistance depends on the tool used and the interconnection length, refer to the tool do cument when selecting a pull-up resistor. rst pin connect the rst pin to an external pull-up resistor of 2 k ? or above. to prevent the device from unintentionally entering the reset mode due to noise, minimize the interconnection length between a pull-up resistor and the rst pin and that between a pull-up resistor and the v cc pin when designing the layout of the printed circuit board. the pf2/rst pin functions as the reset input/output pin after power-on. in addition, the re set output of the pf2/rst pin can be enabled by the rstoe bit in the sysc regi ster, and the reset input function and the general purpose i/o fu nction can be selected by the rsten bit in the sysc register. c pin use a ceramic capacitor or a capacitor with equivalent fre quency characteristics. the decoupling capacitor for the v cc pin must have a capacitance equal to or larger than the capacitance of c s . for the connection to a decoupling capacitor c s , see the diagram below. to prevent the device from uninte ntionally entering a mode to which the device is not set to transit due to noise, minimize the distance between the c pin and c s and the distance between c s and the v ss pin when designing the layout of a printed circuit board. note on serial communication in serial communication, reception of wrong data may occur due to noise or other causes. therefor e, design a printed circuit bo ard to prevent noise from occu rring. taking account of the recept ion of wrong data, take measures such as adding a checksum to the end of data in order to detect errors. if an error is detected, retransmit the data. c cs dbg rst dbg/rst /c pins connection diagram
document number: 002-04696 rev. *a page 20 of 105 mb95650l series 10. block diagram reset with lvd dual operation flash with security function (36/20/12/8 kbyte) f 2 mc-8fx cpu ram (1024/512/256 bytes) oscillator circuit cr oscillator clock control on-chip debug wild register external interrupt lin-uart internal bus 8/16-bit composite timer ch. 0 i 2 c bus interface ch. 0 8/16-bit composite timer ch. 1 8/12-bit a/d converter port port pf2 *1 /rst *2 pf0/x0 *2 pf1/x1 *2 pg1/x0a *2 pg2/x1a *2 p02/int02 to p07/int07 c (p02/sck) (p03/sot) (p04/sin) (p00/an00 to p05 *3 /an05) (p12 *1 /dbg) (p05/to00) (p06/to01) (p04/ec0), p12 *1 /ec0 uart/sio ch. 0 p17/ui0 p62/uck0 p16/uo0 (p62 *3 /to10), p62 *3 /to10 p63 *3 /to11 p64/ec1 p14* 1 /sda0 p15* 1 /scl0 i 2 c bus interface ch. 1 (p16/sda1) (p17/scl1) vcc vss *1: *2: *3: p12, p14, p15 and pf2 are n-ch open drain pins. software select p05 to p07, p62 and p63 are high-current pins. note: pins in parentheses indicate that those pins are shared among different peripheral functions.
document number: 002-04696 rev. *a page 21 of 105 mb95650l series 11. cpu core memory space the memory space of the mb95650l series is 64 kbyte in size, and consists of an i/o area, an extended i/o area, a data area, an d a program area. the memory space includes areas intended for spec ific purposes such as general-purpose registers and a vector table. the memory maps of the mb95650l series are shown below. memory maps mb95f653e/f653l mb95f654e/f654l mb95f652e/f652l i/o area access prohibited ram 256 bytes registers access prohibited extended i/o area access prohibited flash memory 4 kbyte flash memory 4 kbyte 0x0000 0x0080 0x0090 0x0100 0x0190 0x0f80 0x1000 0x2000 0xf000 0xffff i/o area access prohibited 0x0000 0x0080 0x0090 i/o area access prohibited 0x0000 0x0080 0x0090 registers 0x0100 0x0200 0x0290 registers 0x0100 0x0200 access prohibited extended i/o area flash memory 4 kbyte 0x0f80 0x1000 0x2000 flash memory 4 kbyte 0x1000 0x2000 flash memory 4 kbyte extended i/o area 0x0f80 0x1000 access prohibited ram 512 bytes access prohibited flash memory 8 kbyte 0xe000 0xffff access prohibited 0x8000 0x2000 access prohibited 0xc000 ram 1024 bytes flash memory 16 kbyte 0x0490 0xffff mb95f656e/f656l i/o area access prohibited 0x0000 0x0080 0x0090 registers 0x0100 0x0200 extended i/o area 0x0f80 access prohibited ram 1024 bytes flash memory 32 kbyte 0x0490 0xffff
document number: 002-04696 rev. *a page 22 of 105 mb95650l series 12. memory space the memory space of the mb95650l series is 64 kbyte in size, and consists of an i/o area, an extended i/o area, a data area, an d a program area. the memory space includes areas for specific app lications such as general-purpose registers and a vector table. i/o area (addresses: 0x0000 to 0x007f) ? this area contains the control registers and data registers for built-in peripheral functions. ? as the i/o area forms part of the memory space, it can be accessed in the same way as the memory. it can also be accessed at high-speed by using direct addressing instructions. extended i/o area (addresses: 0x0f80 to 0x0fff) ? this area contains the control registers and data registers for built-in peripheral functions. ? as the extended i/o area forms part of the memory space, it can be accessed in the same way as the memory. data area ? static ram is incorporated in the data area as the internal data area. ? the internal ram size varies according to product. ? the ram area from 0x0090 to 0x00ff can be accessed at high-speed by using direct addressing instructions. ? in mb95f656e/f656l, the area from 0x0090 to 0x047f is an exte nded direct addressing area. it can be accessed at high-speed by direct addressing instructi ons with a direct bank pointer set. ? in mb95f654e/f654l, the area from 0x0090 to 0x047f is an exte nded direct addressing area. it can be accessed at high-speed by direct addressing instructi ons with a direct bank pointer set. ? in mb95f653e/f653l, the area from 0x0090 to 0x028f is an exte nded direct addressing area. it can be accessed at high-speed by direct addressing instructi ons with a direct bank pointer set. ? in mb95f652e/f652l, the area from 0x0090 to 0x018f is an exte nded direct addressing area. it can be accessed at high-speed by direct addressing instructi ons with a direct bank pointer set. ? in mb95f653e/f653l/f654e/f654l/f656e/f656l, the area from 0x0100 to 0x01ff can be used as a general-purpose register area. ? in mb95f652e/f652l, the area from 0x0100 to 0x018f can be used as a general-purpose register area. program area ? the flash memory is incorporated in the program area as the internal program area. ? the flash memory size varies according to product. ? the area from 0xffc0 to 0xffff is used as the vector table. ? the area from 0xffbb to 0xffbf is used to store data of the non-volatile register.
document number: 002-04696 rev. *a page 23 of 105 mb95650l series memory space map direct addressing area extended direct addressing area i/o area access prohibited 0x0000 0x0080 0x0090 registers (general-purpose register area) 0x0100 0x0200 0x047f vector table area extended i/o area 0x0f80 0x0fff 0x1000 access prohibited program area data area 0x048f 0x0490 0xffff 0xffc0
document number: 002-04696 rev. *a page 24 of 105 mb95650l series 13. areas for specific applications the general-purpose register area and vector tabl e area are used for the specific applications. general-purpose register area (addresses: 0x0100 to 0x01ff* 1 ) ? this area contains the auxiliary registers used for 8-bit arithmetic operations, transfer, etc. ? as this area forms part of the ram area, it can also be used as conventional ram. ? when the area is used as general-purpose re gisters, general-purpose register addressi ng enables high-speed access with short instructions. non-volatile register data area (addresses: 0xffbb to 0xffbf) ? the area from 0xffbb to 0xffbf is used to store data of the n on-volatile register. for details, refer to ?chapter 23 non-volat ile register (nvr) interface? in ?new 8fx mb95650l series hardware manual?. vector table area (addresses: 0xffc0 to 0xffff) ? this area is used as the vector table for vector call instructions (callv), interrupts, and resets. ? the top of the flash memory area is allocated to the vector ta ble area. the start address of a service routine is set to an ad dress in the vector table in the form of data. ?16. interrupt source table? lists the vector table addresses corresponding to vector call instructions, interrupts, and resets . for details, refer to ?chapter 4 reset?, ?chapter 5 interrupts? and ?a.2 special instruction s pecial instruction callv #vct? in ?new 8fx mb95650l series hardware manual?. direct bank pointer and access area *1: due to the memory size limit, the available access area is up to ?0x018f? in mb95f652e/f652l. *2: due to the memory size limit, the available access area is up to ?0x028f? in mb95f653e/f653l. direct bank pointer (dp[2:0]) operand-specified dir access area 0bxxx (it does not affect mapping.) 0x0000 to 0x007f 0x0000 to 0x007f 0b000 (initial value) 0x0090 to 0x00ff 0x0090 to 0x00ff 0b001 0x0080 to 0x00ff 0x0100 to 0x017f 0b010 0x0180 to 0x01ff* 1 0b011 0x0200 to 0x027f 0b100 0x0280 to 0x02ff* 2 0b101 0x0300 to 0x037f 0b110 0x0380 to 0x03ff 0b111 0x0400 to 0x047f
document number: 002-04696 rev. *a page 25 of 105 mb95650l series 14. i/o map (continued) address register abbreviation register name r/w initial value 0x0000 pdr0 port 0 data register r/w 0b00000000 0x0001 ddr0 port 0 direction register r/w 0b00000000 0x0002 pdr1 port 1 data register r/w 0b00000000 0x0003 ddr1 port 1 direction register r/w 0b00000000 0x0004 ? (disabled) ? ? 0x0005 watr oscillation stabilization wait time setting register r/w 0b11111111 0x0006 pllc pll control register r/w 0b000x0000 0x0007 sycc system clock control register r/w 0bxxx11011 0x0008 stbc standby control register r/w 0b00000000 0x0009 rsrr reset source register r/w 0b000xxxxx 0x000a tbtc time-base timer control register r/w 0b00000000 0x000b wpcr watch prescaler control register r/w 0b00000000 0x000c wdtc watchdog timer control register r/w 0b00xx0000 0x000d sycc2 system clock control register 2 r/w 0bxxxx0011 0x000e to 0x0015 ? (disabled) ? ? 0x0016 pdr6 port 6 data register r/w 0b00000000 0x0017 ddr6 port 6 direction register r/w 0b00000000 0x0018 to 0x0027 ? (disabled) ? ? 0x0028 pdrf port f data register r/w 0b00000000 0x0029 ddrf port f direction register r/w 0b00000000 0x002a pdrg port g data register r/w 0b00000000 0x002b ddrg port g direction register r/w 0b00000000 0x002c pul0 port 0 pull-up register r/w 0b00000000 0x002d to 0x0032 ? (disabled) ? ? 0x0033 pul6 port 6 pull-up register r/w 0b00000000 0x0034 ? (disabled) ? ? 0x0035 pulg port g pull-up register r/w 0b00000000 0x0036 t01cr1 8/16-bit composite timer 01 status control register 1 r/w 0b00000000 0x0037 t00cr1 8/16-bit composite timer 00 status control register 1 r/w 0b00000000 0x0038 t11cr1 8/16-bit composite timer 11 status control register 1 r/w 0b00000000 0x0039 t10cr1 8/16-bit composite timer 10 status control register 1 r/w 0b00000000 0x003a to 0x0048 ? (disabled) ? ?
document number: 002-04696 rev. *a page 26 of 105 mb95650l series (continued) address register abbreviation register name r/w initial value 0x0049 eic10 external interrupt circuit co ntrol register ch. 2/ch. 3 r/w 0b00000000 0x004a eic20 external interrupt circuit co ntrol register ch. 4/ch. 5 r/w 0b00000000 0x004b eic30 external interrupt circuit co ntrol register ch. 6/ch. 7 r/w 0b00000000 0x004c to 0x004e ? (disabled) ? ? 0x004f lvdc lvd control register r/w 0b00000100 0x0050 scr lin-uart serial control register r/w 0b00000000 0x0051 smr lin-uart serial mode register r/w 0b00000000 0x0052 ssr lin-uart serial status register r/w 0b00001000 0x0053 rdr lin-uart receive data register r/w 0b00000000 tdr lin-uart transmit data register 0x0054 escr lin-uart extended status control register r/w 0b00000100 0x0055 eccr lin-uart extended communica tion control register r/w 0b000000xx 0x0056 smc10 uart/sio serial mode c ontrol register 1 ch. 0 r/w 0b00000000 0x0057 smc20 uart/sio serial mode c ontrol register 2 ch. 0 r/w 0b00100000 0x0058 ssr0 uart/sio serial status and data register ch. 0 r/w 0b00000001 0x0059 tdr0 uart/sio serial output data register ch. 0 r/w 0b00000000 0x005a rdr0 uart/sio serial input data register ch. 0 r 0b00000000 0x005b to 0x005f ? (disabled) ? ? 0x0060 ibcr00 i 2 c bus control register 0 ch. 0 r/w 0b00000000 0x0061 ibcr10 i 2 c bus control register 1 ch. 0 r/w 0b00000000 0x0062 ibsr0 i 2 c bus status register ch. 0 r/w 0b00000000 0x0063 iddr0 i 2 c data register ch. 0 r/w 0b00000000 0x0064 iaar0 i 2 c address register ch. 0 r/w 0b00000000 0x0065 iccr0 i 2 c clock control register ch. 0 r/w 0b00000000 0x0066 ibcr01 i 2 c bus control register 0 ch. 1 r/w 0b00000000 0x0067 ibcr11 i 2 c bus control register 1 ch. 1 r/w 0b00000000 0x0068 ibsr1 i 2 c bus status register ch. 1 r/w 0b00000000 0x0069 iddr1 i 2 c data register ch. 1 r/w 0b00000000 0x006a iaar1 i 2 c address register ch. 1 r/w 0b00000000 0x006b iccr1 i 2 c clock control register ch. 1 r/w 0b00000000 0x006c adc1 8/12-bit a/d converter control register 1 r/w 0b00000000 0x006d adc2 8/12-bit a/d converter control register 2 r/w 0b00000000 0x006e addh 8/12-bit a/d converter data register (upper) r/w 0b00000000 0x006f addl 8/12-bit a/d converter data register (lower) r/w 0b00000000 0x0070 adc3 8/12-bit a/d converter control register 3 r/w 0b01111100
document number: 002-04696 rev. *a page 27 of 105 mb95650l series (continued) address register abbreviation register name r/w initial value 0x0071 fsr2 flash memory status register 2 r/w 0b00000000 0x0072 fsr flash memory status register r/w 0b000x0000 0x0073 swre0 flash memory sector write control register 0 r/w 0b00000000 0x0074 fsr3 flash memory status register 3 r 0b000xxxxx 0x0075 fsr4 flash memory status register 4 r/w 0b00000000 0x0076 wren wild register address compare enable register r/w 0b00000000 0x0077 wror wild register data test setting register r/w 0b00000000 0x0078 ? mirror of register bank pointer (rp) and direct bank pointer (dp) ? ? 0x0079 ilr0 interrupt level setting register 0 r/w 0b11111111 0x007a ilr1 interrupt level setting register 1 r/w 0b11111111 0x007b ilr2 interrupt level setting register 2 r/w 0b11111111 0x007c ilr3 interrupt level setting register 3 r/w 0b11111111 0x007d ilr4 interrupt level setting register 4 r/w 0b11111111 0x007e ilr5 interrupt level setting register 5 r/w 0b11111111 0x007f ? (disabled) ? ? 0x0f80 wrarh0 wild register address setting register (upper) ch. 0 r/w 0b00000000 0x0f81 wrarl0 wild register address setting register (lower) ch. 0 r/w 0b00000000 0x0f82 wrdr0 wild register data se tting register ch. 0 r/w 0b00000000 0x0f83 wrarh1 wild register address setting register (upper) ch. 1 r/w 0b00000000 0x0f84 wrarl1 wild register address setting register (lower) ch. 1 r/w 0b00000000 0x0f85 wrdr1 wild register data se tting register ch. 1 r/w 0b00000000 0x0f86 wrarh2 wild register address setting register (upper) ch. 2 r/w 0b00000000 0x0f87 wrarl2 wild register address setting register (lower) ch. 2 r/w 0b00000000 0x0f88 wrdr2 wild register data se tting register ch. 2 r/w 0b00000000 0x0f89 to 0x0f91 ? (disabled) ? ? 0x0f92 t01cr0 8/16-bit composite timer 01 status control register 0 r/w 0b00000000 0x0f93 t00cr0 8/16-bit composite timer 00 status control register 0 r/w 0b00000000 0x0f94 t01dr 8/16-bit composite timer 01 data register r/w 0b00000000 0x0f95 t00dr 8/16-bit composite timer 00 data register r/w 0b00000000 0x0f96 tmcr0 8/16-bit composite timer 00/01 timer mode control register r/w 0b00000000 0x0f97 t11cr0 8/16-bit composite timer 11 status control register 0 r/w 0b00000000 0x0f98 t10cr0 8/16-bit composite timer 10 status control register 0 r/w 0b00000000 0x0f99 t11dr 8/16-bit composite timer 11 data register r/w 0b00000000 0x0f9a t10dr 8/16-bit composite timer 10 data register r/w 0b00000000 0x0f9b tmcr1 8/16-bit composite timer 10/11 timer mode control register r/w 0b00000000
document number: 002-04696 rev. *a page 28 of 105 mb95650l series (continued) r/w access symbols initial value symbols note: do not write to an address that is ?(disabled)?. if a ?(disabled)? address is read, an indeterminate value is returned. address register abbreviation register name r/w initial value 0x0f9c to 0x0fbb ? (disabled) ? ? 0x0fbc bgr1 lin-uart baud rate generator register 1 r/w 0b00000000 0x0fbd bgr0 lin-uart baud rate generator register 0 r/w 0b00000000 0x0fbe pssr0 uart/sio dedicated baud rate generat or prescaler select register ch. 0 r/w 0b00000000 0x0fbf brsr0 uart/sio dedicated baud rate generat or baud rate setting register ch. 0 r/w 0b00000000 0x0fc0 to 0x0fc2 ? (disabled) ? ? 0x0fc3 aidrl a/d input disable register (lower) r/w 0b00000000 0x0fc4 to 0x0fe3 ? (disabled) ? ? 0x0fe4 crth main cr clock trimming register (upper) r/w 0b000xxxxx 0x0fe5 crtl main cr clock trimming register (lower) r/w 0b000xxxxx 0x0fe6 sysc2 system configuration register 2 r/w 0b00000000 0x0fe7 crtda main cr clock temperature dependent adjustment register r/w 0b000xxxxx 0x0fe8 sysc system configuration register r/w 0b00111111 0x0fe9 cmcr clock monitoring control register r/w 0b00000000 0x0fea cmdr clock monitoring data register r 0b00000000 0x0feb wdth watchdog timer selection id register (upper) r 0bxxxxxxxx 0x0fec wdtl watchdog timer select ion id register (lower) r 0bxxxxxxxx 0x0fed to 0x0fff ? (disabled) ? ? r/w : readable/writable r : read only 0 : the initial value of this bit is ?0?. 1 : the initial value of this bit is ?1?. x : the initial value of this bit is undefined.
document number: 002-04696 rev. *a page 29 of 105 mb95650l series 15. i/o ports list of port registers r/w : readable/writable (the read value is the same as the write value.) r, rm/w : readable/writable (the read value is different from the write value. the writ e value is read by the read-modify-write (rmw) type of instruction.) register name read/write initial value port 0 data register pdr0 r, rm/w 0b00000000 port 0 direction register ddr0 r/w 0b00000000 port 1 data register pdr1 r, rm/w 0b00000000 port 1 direction register ddr1 r/w 0b00000000 port 6 data register pdr6 r, rm/w 0b00000000 port 6 direction register ddr6 r/w 0b00000000 port f data register pdrf r, rm/w 0b00000000 port f direction register ddrf r/w 0b00000000 port g data register pdrg r, rm/w 0b00000000 port g direction register ddrg r/w 0b00000000 port 0 pull-up register pul0 r/w 0b00000000 port 6 pull-up register pul6 r/w 0b00000000 port g pull-up register pulg r/w 0b00000000 a/d input disable register (lower) aidrl r/w 0b00000000
document number: 002-04696 rev. *a page 30 of 105 mb95650l series 15.1 port 0 port 0 is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of perip heral functions, refer to their respective chapters in ?new 8fx mb95650l series hardware manual?. 15.1.1 port 0 configuration port 0 is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port 0 data register (pdr0) ? port 0 direction register (ddr0) ? port 0 pull-up register (pul0) ? a/d input disable register (lower) (aidrl) 15.1.2 block diagrams of port 0 p00/an00 pin this pin has the following peripheral function: ? 8/12-bit a/d converter analog input pin (an00) p01/an01 pin this pin has the following peripheral function: ? 8/12-bit a/d converter analog input pin (an01) block diagram of p00/an00 and p01/an01 pdr0 pin pdr0 read pdr0 write executing bit manipulation instruction ddr0 read ddr0 write pul0 read pul0 write aidrl read aidrl write ddr0 pul0 aidrl 0 1 stop mode, watch mode (spl = 1) a/d analog input hysteresis pull-up internal bus
document number: 002-04696 rev. *a page 31 of 105 mb95650l series p02/int02/an02/sck pin this pin has the following peripheral functions: ? external interrupt input pin (int02) ? 8/12-bit a/d converter analog input pin (an02) ? lin-uart clock i/o pin (sck) p03/int03/an03/sot pin this pin has the following peripheral functions: ? external interrupt input pin (int03) ? 8/12-bit a/d converter analog input pin (an03) ? lin-uart data output pin (sot) p05/int05/an05/to00 pin this pin has the following peripheral functions: ? external interrupt input pin (int05) ? 8/12-bit a/d converter analog input pin (an05) ? 8/16-bit composite timer ch. 0 output pin (to00) block diagram of p02/int02/an02/sck, p03/int03/an03/sot and p05/int05/an05/to00 pdr0 pin pdr0 read pdr0 write executing bit manipulation instruction ddr0 read ddr0 write pul0 read pul0 write aidrl read aidrl write ddr0 pul0 aidrl 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable (int02, int03 and int05) peripheral function output enable peripheral function output a/d analog input hysteresis pull-up internal bus
document number: 002-04696 rev. *a page 32 of 105 mb95650l series p04/int04/an04/sin/ec0 pin this pin has the following peripheral functions: ? external interrupt input pin (int04) ? 8/12-bit a/d converter analog input pin (an04) ? lin-uart data input pin (sin) ? 8/16-bit composite timer ch. 0 clock input pin (ec0) block diagram of p04/int04/an04/sin/ec0 pdr0 pin pdr0 read pdr0 write executing bit manipulation instruction ddr0 read ddr0 write pul0 read pul0 write aidrl read aidrl write ddr0 pul0 aidrl 0 1 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable (int04) a/d analog input cmos pull-up internal bus
document number: 002-04696 rev. *a page 33 of 105 mb95650l series p06/int06/to01 pin this pin has the following peripheral functions: ? external interrupt input pin (int06) ? 8/16-bit composite timer ch. 0 output pin (to01) p07/int07/to10 pin this pin has the following peripheral functions: ? external interrupt input pin (int07) ? 8/16-bit composite timer ch. 1 output pin (to10) block diagram of p06/int06/to01 and p07/int07/to10 pdr0 pin pdr0 read pdr0 write executing bit manipulation instruction ddr0 read ddr0 write pul0 read pul0 write ddr0 pul0 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable (int06 and int07) peripheral function output enable peripheral function output hysteresis pull-up internal bus
document number: 002-04696 rev. *a page 34 of 105 mb95650l series 15.1.3 port 0 registers port 0 register functions correspondence between registers and pins for port 0 register abbreviation data read read by read-modify-write (rmw) instruction write pdr0 0 pin state is ?l? level. pdr0 value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdr0 value is ?1?. as output port, outputs ?h? level. ddr0 0 port input enabled 1 port output enabled pul0 0 pull-up disabled 1 pull-up enabled aidrl 0 analog input enabled 1 port input enabled correspondence between related register bits and pins pin name p07 p06 p05 p04 p03 p02 p01 p00 pdr0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ddr0 pul0 aidrl - -
document number: 002-04696 rev. *a page 35 of 105 mb95650l series 15.1.4 port 0 operations operation as an output port ? a pin becomes an output port if t he bit in the ddr0 register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdr0 register to external pins. ? if data is written to the pdr0 register, the value is stored in the output latch and is output to the pin set as an output por t as it is. ? reading the pdr0 register returns the pdr0 register value. operation as an input port ? a pin becomes an input port if the bit in the ddr0 register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when using a pin shared with the analog input function as an in put port, set the corresponding bit in the a/d input disable re gister (lower) (aidrl) to ?1?. ? if data is written to the pdr0 register, the value is stored in the output latch but is not output to the pin set as an input port. ? reading the pdr0 register returns the pin value. however, if the read-modify-write (rmw) type of instruction is used to read the pdr0 register, the pdr0 register value is returned. operation as a peripheral function output pin ? a pin becomes a peripheral func tion output pin if the peripheral output function is enabled by setting the output enable bit o f a peripheral function corresponding to that pin. ? the pin value can be read from the pdr0 register even if the per ipheral function output is enabl ed. therefore, the output valu e of a peripheral function can be read by the read operation on t he pdr0 register. however, if the read-modify-write (rmw) type of instruction is used to read the pdr0 re gister, the pdr0 register value is returned. operation as a peripheral function input pin ? to set a pin as an input port, set the bit in the ddr0 register corresponding to the input pin of a peripheral function to ?0? . ? when using a pin shared with the analog input function as another peripheral function input pin, configure it as an input port by setting the bit in the aidrl register corresponding to that pin to ?1?. ? reading the pdr0 register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin. however, if the read-modify-write (rmw) type of instruction is used to read the pdr0 register, the pdr0 register value is re- turned. operation at reset if the cpu is reset, all bits in the ddr0 register are initiali zed to ?0? and port input is enabled. as for a pin shared with a nalog input, its port input is disabled because the aidrl register is initialized to ?0?. operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (s tbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the ddr0 register value. the input of that pin is locked to ?l? level and blocked in order to prevent lea ks due to input open. however, if the interrupt input is enabled for the external interrupt (int02 to int07), the input is enabled and not blocked. ? if the pin state setting bit is ?0?, the st ate of the port i/o or that of the peripheral function i/o remains unchanged and th e output level is maintained. operation as an analog input pin ? set the bit in the ddr0 register bit corresponding to the analog input pin to ?0? and the bit corresponding to that pin in the aidrl register to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. in addition, set the corres pond- ing bit in the pul0 register to ?0?. operation as an external interrupt input pin ? set the bit in the ddr0 register corresponding to the external interrupt input pin to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? the pin value is always input to the external interrupt circuit. when using a pin for a function other than the interrupt, dis able the external interrupt function corresponding to that pin. operation of the pull-up register setting the bit in the pul0 register to ?1? makes the pull-up resi stor be internally connected to the pin. when the pin output is ?l? level, the pull-up resistor is disconnected re gardless of the value of the pul0 register.
document number: 002-04696 rev. *a page 36 of 105 mb95650l series 15.2 port 1 port 1 is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of perip heral functions, refer to their respective chapters in ?new 8fx mb95650l series hardware manual?. 15.2.1 port 1 configuration port 1 is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port 1 data register (pdr1) ? port 1 direction register (ddr1) 15.2.2 (2)block diagrams of port 1 p12/dbg/ec0 pin this pin has the following peripheral functions: ? dbg input pin (dbg) ? 8/16-bit composite timer ch. 0 clock input pin (ec0) block diagram of p12/dbg/ec0 pdr1 pin pdr1 read pdr1 write executing bit manipulation instruction ddr1 read ddr1 write ddr1 0 1 stop mode, watch mode (spl = 1) od hysteresis internal bus peripheral function input
document number: 002-04696 rev. *a page 37 of 105 mb95650l series p14/sda0 pin this pin has the following peripheral function: ?i 2 c bus interface ch. 0 data i/o pin (sda0) p15/scl0 pin this pin has the following peripheral function: ?i 2 c bus interface ch. 0 clock i/o pin (scl0) block diagram of p14/sda0 and p15/scl0 pdr1 pdr1 read pdr1 write executing bit manipulation instruction ddr1 read ddr1 write ddr1 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable peripheral function output enable peripheral function output cmos pin od internal bus
document number: 002-04696 rev. *a page 38 of 105 mb95650l series p16/sda1/uo0 pin this pin has the following peripheral functions: ?i 2 c bus interface ch. 1 data i/o pin (sda1) ? uart/sio ch. 0 data output pin (uo0) block diagram of p16/sda1/uo0 pdr1 pdr1 read pdr1 write executing bit manipulation instruction ddr1 read ddr1 write ddr1 0 1 1 0 stop mode, watch mode (spl = 1) internal bus peripheral function input enable peripheral function input peripheral function output enable peripheral function output i 2 c function input i 2 c function input enable i 2 c function output enable i 2 c function output uart/sio function output enable i2c_sel bit in sysc2 register uart/sio function output cmos pin n-ch p-ch 0 1
document number: 002-04696 rev. *a page 39 of 105 mb95650l series p17/scl1/ui0 pin this pin has the following peripheral functions: ?i 2 c bus interface ch. 1 clock i/o pin (scl1) ? uart/sio ch. 0 data input pin (ui0) block diagram of p17/scl1/ui0 pdr1 pdr1 read pdr1 write executing bit manipulation instruction ddr1 read ddr1 write ddr1 0 1 1 0 stop mode, watch mode (spl = 1) internal bus peripheral function input enable peripheral function input peripheral function output enable peripheral function output i 2 c function input i 2 c function input enable i 2 cfunction output enable i 2 c function output uart/sio function input enable i2c_sel bit in sysc2 register uart/sio function input cmos pin n-ch p-ch 0 1
document number: 002-04696 rev. *a page 40 of 105 mb95650l series 15.2.3 port 1 registers port 1 register functions *: if the pin is an n-ch open drain pin, the pin state becomes hi-z. correspondence between registers and pins for port 1 register abbreviation data read read by read-modify-write (rmw) instruction write pdr1 0 pin state is ?l? level. pdr1 value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdr1 value is ?1?. as output port, outputs ?h? level.* ddr1 0 port input enabled 1 port output enabled correspondence between related register bits and pins pin name p17 p16 p15 p14 - p12 - - pdr1 bit7 bit6 bit5 bit4 - bit2 - - ddr1
document number: 002-04696 rev. *a page 41 of 105 mb95650l series 15.2.4 port 1 operations operation as an output port ? a pin becomes an output port if t he bit in the ddr1 register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdr1 register to external pins. ? if data is written to the pdr1 register, the value is stored in the output latch and is output to the pin set as an output por t as it is. ? reading the pdr1 register returns the pdr1 register value. operation as an input port ? a pin becomes an input port if the bit in the ddr1 register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdr1 register, the value is stored in the output latch but is not output to the pin set as an input port. ? reading the pdr1 register returns the pin value. however, if the read-modify-write (rmw) type of instruction is used to read the pdr1 register, the pdr1 register value is returned. operation as a peripheral function output pin ? a pin becomes a peripheral func tion output pin if the peripheral output function is enabled by setting the output enable bit o f a peripheral function corresponding to that pin. ? the pin value can be read from the pdr1 register even if the per ipheral function output is enabl ed. therefore, the output valu e of a peripheral function can be read by the read operation on t he pdr1 register. however, if the read-modify-write (rmw) type of instruction is used to read the pdr1 re gister, the pdr1 register value is returned. operation as a peripheral function input pin ? to set a pin as an input port, set the bit in the ddr1 register corresponding to the input pin of a peripheral function to ?0? . ? reading the pdr1 register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin. however, if the read-modify-write (rmw) type of instruction is used to read the pdr1 register, the pdr1 register value is returned. operation at reset if the cpu is reset, all bits in the ddr1 register are initialized to ?0? and port input is enabled. operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (s tbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the ddr1 register value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. ? if the pin state setting bit is ?0?, the st ate of the port i/o or that of the peripheral function i/o remains unchanged and th e output level is maintained.
document number: 002-04696 rev. *a page 42 of 105 mb95650l series 15.3 port 6 port 6 is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of perip heral functions, refer to their respective chapters in ?new 8fx mb95650l series hardware manual?. 15.3.1 port 6 configuration port 6 is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port 6 data register (pdr6) ? port 6 direction register (ddr6) ? port 6 pull-up register (pul6) 15.3.2 block diagrams of port 6 p62/to10/uck0 pin this pin has the following peripheral functions: ? 8/16-bit composite timer ch. 1 output pin (to10) ? uart/sio ch. 0 clock i/o pin (uck0) p63/to11 pin this pin has the following peripheral function: ? 8/16-bit composite timer ch. 1 output pin (to11) block diagram of p62/ to10/uck0 and p63/to11 pdr6 pin pdr6 read pdr6 write executing bit manipulation instruction ddr6 read ddr6 write pul6 read pul6 write ddr6 pul6 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable peripheral function output enable peripheral function output hysteresis pull-up internal bus
document number: 002-04696 rev. *a page 43 of 105 mb95650l series p64/ec1 pin this pin has the following peripheral function: ? 8/16-bit composite timer ch. 1 clock input pin (ec1) block diagram of p64/ec1 pdr6 pin pdr6 read pdr6 write executing bit manipulation instruction ddr6 read ddr6 write ddr6 0 1 stop mode, watch mode (spl = 1) peripheral function input hysteresis internal bus
document number: 002-04696 rev. *a page 44 of 105 mb95650l series 15.3.3 port 6 registers port 6 register functions *: if the pin is an n-ch open drain pin, the pin state becomes hi-z. correspondence between registers and pins for port 6 register abbreviation data read read by read-modify-write (rmw) instruction write pdr6 0 pin state is ?l? level. pdr6 value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdr6 value is ?1?. as output port, outputs ?h? level.* ddr6 0 port input enabled 1 port output enabled pul6 0 pull-up disabled 1 pull-up enabled correspondence between related register bits and pins pin name - - - p64 p63 p62 - - pdr6 - - - bit4 bit3 bit2 - - ddr6 pul6
document number: 002-04696 rev. *a page 45 of 105 mb95650l series 15.3.4 port 6 operations operation as an output port ? a pin becomes an output port if t he bit in the ddr6 register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdr6 register to external pins. ? if data is written to the pdr6 register, the value is stored in the output latch and is output to the pin set as an output por t as it is. ? reading the pdr6 register returns the pdr6 register value. operation as an input port ? a pin becomes an input port if the bit in the ddr6 register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdr6 register, the value is stored in the output latch but is not output to the pin set as an input port. ? reading the pdr6 register returns the pin value. however, if the read-modify-write (rmw) type of instruction is used to read the pdr6 register, the pdr6 register value is returned. operation as a peripheral function output pin ? a pin becomes a peripheral func tion output pin if the peripheral output function is enabled by setting the output enable bit o f a peripheral function corresponding to that pin. ? the pin value can be read from the pdr6 register even if the per ipheral function output is enabl ed. therefore, the output valu e of a peripheral function can be read by the read operation on t he pdr6 register. however, if the read-modify-write (rmw) type of instruction is used to read the pdr6 re gister, the pdr6 register value is returned. operation as a peripheral function input pin ? to set a pin as an input port, set the bit in the ddr6 register corresponding to the input pin of a peripheral function to ?0? . ? reading the pdr6 register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin. however, if the read-modify-write (rmw) type of instruction is used to read the pdr6 register, the pdr6 register value is re- turned. operation at reset if the cpu is reset, all bits in the ddr6 register are initialized to ?0? and port input is enabled. operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (s tbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the ddr6 register value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. ? if the pin state setting bit is ?0?, the st ate of the port i/o or that of the peripheral function i/o remains unchanged and th e output level is maintained. operation of the pull-up register setting the bit in the pul6 register to ?1? makes the pull-up resi stor be internally connected to the pin. when the pin output is ?l? level, the pull-up resistor is disconnected re gardless of the value of the pul6 register.
document number: 002-04696 rev. *a page 46 of 105 mb95650l series 15.4 port f port f is a general-purpose i/o port. this section focuses on it s functions as a general-purpose i/o port. for details of perip heral functions, refer to their respective chapters in ?new 8fx mb95650l series hardware manual?. 15.4.1 port f configuration port f is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port f data register (pdrf) ? port f direction register (ddrf) 15.4.2 block diagrams of port f pf0/x0 pin this pin has the following peripheral function: ? main clock input oscillation pin (x0) pf1/x1 pin this pin has the following peripheral function: ? main clock i/o oscillation pin (x1) block diagram of pf0/x0 and pf1/x1 pdrf pin pdrf read pdrf write executing bit manipulation instruction ddrf read ddrf write ddrf 0 1 stop mode, watch mode (spl = 1) internal bus hysteresis
document number: 002-04696 rev. *a page 47 of 105 mb95650l series pf2/rst pin this pin has the following peripheral function: ? reset pin (rst ) block diagram of pf2/rst pdrf pdrf read pdrf write executing bit manipulation instruction ddrf read ddrf write ddrf 0 1 1 0 stop mode, watch mode (spl = 1) reset input reset input enable reset output enable reset output pin od internal bus hysteresis
document number: 002-04696 rev. *a page 48 of 105 mb95650l series 15.4.3 port f registers port f register functions *: if the pin is an n-ch open drain pin, the pin state becomes hi-z. correspondence between registers and pins for port f *: pf2/rst is the dedicated reset pin on mb95f652l/f653l/f654l/f656l. register abbreviation data read read by read-modify-write (rmw) instruction write pdrf 0 pin state is ?l? level. pdrf value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdrf value is ?1?. as output port, outputs ?h? level.* ddrf 0 port input enabled 1 port output enabled correspondence between related register bits and pins pin name - - - - - pf2* pf1 pf0 pdrf -----bit2bit1bit0 ddrf
document number: 002-04696 rev. *a page 49 of 105 mb95650l series 15.4.4 port f operations operation as an output port ? a pin becomes an output port if t he bit in the ddrf register correspon ding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdrf register to external pins. ? if data is written to the pdrf register, the value is stored in the output latch and is output to the pin set as an output por t as it is. ? reading the pdrf register returns the pdrf register value. operation as an input port ? a pin becomes an input port if the bit in the ddrf register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdrf register, t he value is stored in the output latch but is not output to the pin set as an input port. ? reading the pdrf register returns the pin value. however, if the read-modify-write (rmw) type of instruction is used to read the pdrf register, the pdrf register value is returned. operation at reset if the cpu is reset, all bits in the ddrf register are initialized to ?0? and port input is enabled. operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (s tbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the ddrf register value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. ? if the pin state setting bit is ?0?, the st ate of the port i/o or that of the peripheral function i/o remains unchanged and th e output level is maintained.
document number: 002-04696 rev. *a page 50 of 105 mb95650l series 15.5 port g port g is a general-purpose i/o port. this section focuses on it s functions as a general-purpose i/o port. for details of perip heral functions, refer to their respective chapters in ?new 8fx mb95650l series hardware manual?. 15.5.1 port g configuration port g is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port g data register (pdrg) ? port g direction register (ddrg) ? port g pull-up register (pulg) 15.5.2 block diagram of port g pg1/x0a pin this pin has the following peripheral function: ? subclock input oscillation pin (x0a) pg2/x1a pin this pin has the following peripheral function: ? subclock i/o oscillation pin (x1a) block diagram of pg1/x0a and pg2/x1a pdrg pin pdrg read pdrg write executing bit manipulation instruction ddrg read ddrg write pulg read pulg write ddrg pulg 0 1 stop mode, watch mode (spl = 1) hysteresis pull-up internal bus
document number: 002-04696 rev. *a page 51 of 105 mb95650l series 15.5.3 port g registers port g register functions correspondence between registers and pins for port g register abbreviation data read read by read-modify-write (rmw) instruction write pdrg 0 pin state is ?l? level. pdrg value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdrg value is ?1?. as output port, outputs ?h? level. ddrg 0 port input enabled 1 port output enabled pulg 0 pull-up disabled 1 pull-up enabled correspondence between related register bits and pins pin name - - - - - pg2 pg1 - pdrg -----bit2bit1- ddrg pulg
document number: 002-04696 rev. *a page 52 of 105 mb95650l series 15.5.4 port g operations operation as an output port ? a pin becomes an output port if the bit in the ddrg register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdrg register to external pins. ? if data is written to the pdrg register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdrg register returns the pdrg register value. operation as an input port ? a pin becomes an input port if the bit in the ddrg register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdrg register, the value is stored in the output latch but is not output to the pin set as an input port. ? reading the pdrg register returns the pin va lue. however, if the read-modify-write (r mw) type of instruction is used to read the pdrg register, the pdrg register value is returned. operation at reset if the cpu is reset, all bits in the ddrg register are initialized to ?0? and port input is enabled. operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (s tbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compulsorily made to ent er the high impedance state regardless of th e ddrg register value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. ? if the pin state setting bit is ?0?, the st ate of the port i/o or that of the peripheral function i/o remains unchanged and th e output level is maintained. operation of the pull-up register setting the bit in the pulg register to ?1? makes the pull-up re sistor be internally connected to the pin. when the pin output is ?l? level, the pull-up resistor is disconnected re gardless of the value of the pulg register.
document number: 002-04696 rev. *a page 53 of 105 mb95650l series 16. interrupt source table interrupt source interrupt request number vector table address interrupt level setting register priority order of interrupt sources of the same level (occurring simultaneously) upper lower register bit external interrupt ch. 4 irq00 0xfffa 0xfffb ilr0 l00 [1:0] high low external interrupt ch. 5 irq01 0xfff8 0xfff9 ilr0 l01 [1:0] external interrupt ch. 2 irq02 0xfff6 0xfff7 ilr0 l02 [1:0] external interrupt ch. 6 external interrupt ch. 3 irq03 0xfff4 0xfff5 ilr0 l03 [1:0] external interrupt ch. 7 low-voltage detection interrupt circuit irq04 0xfff2 0xfff3 ilr1 l04 [1:0] uart/sio ch. 0 8/16-bit composite timer ch. 0 (lower) irq05 0xfff0 0xfff1 ilr1 l05 [1:0] 8/16-bit composite timer ch. 0 (upper) irq06 0xffee 0xffef ilr1 l06 [1:0] lin-uart (reception) irq07 0xffec 0xffed ilr1 l07 [1:0] lin-uart (transmission) irq08 0xffea 0xffeb ilr2 l08 [1:0] ? irq09 0xffe8 0xffe9 ilr2 l09 [1:0] i 2 c bus interface ch. 1 irq10 0xffe6 0xffe7 ilr2 l10 [1:0] ? irq11 0xffe4 0xffe5 ilr2 l11 [1:0] ? irq12 0xffe2 0xffe3 ilr3 l12 [1:0] ? irq13 0xffe0 0xffe1 ilr3 l13 [1:0] 8/16-bit composite timer ch. 1 (upper) irq14 0xffde 0xffdf ilr3 l14 [1:0] ? irq15 0xffdc 0xffdd ilr3 l15 [1:0] i 2 c bus interface ch. 0 irq16 0xffda 0xffdb ilr4 l16 [1:0] ? irq17 0xffd8 0xffd9 ilr4 l17 [1:0] 8/12-bit a/d converter irq18 0xffd6 0xffd7 ilr4 l18 [1:0] time-base timer irq19 0xffd4 0xffd5 ilr4 l19 [1:0] watch prescaler irq20 0xffd2 0xffd3 ilr5 l20 [1:0] ? irq21 0xffd0 0xffd1 ilr5 l21 [1:0] 8/16-bit composite timer ch. 1 (lower) irq22 0xffce 0xffcf ilr5 l22 [1:0] flash memory irq23 0xffc c 0xffcd ilr5 l23 [1:0]
document number: 002-04696 rev. *a page 54 of 105 mb95650l series 17. pin states in each mode pin name normal operation sleep mode stop mode watch mode on reset spl=0 spl=1 spl=0 spl=1 pf0/x0 oscillation input oscillation input hi-z hi-z hi-z hi-z ? i/o port* 1 i/o port* 1 - previous state kept - input blocked* 1, * 2 -hi-z - input blocked* 1, * 2 - previous state kept - input blocked* 1, * 2 -hi-z - input blocked* 1, * 2 - hi-z - input enabled* 3 (however, it does not function.) pf1/x1 oscillation input oscillation input hi-z hi-z hi-z hi-z ? i/o port* 1 i/o port* 1 - previous state kept - input blocked* 1, * 2 -hi-z - input blocked* 1, * 2 - previous state kept - input blocked* 1, * 2 -hi-z - input blocked* 1, * 2 - hi-z - input enabled* 3 (however, it does not function.) pf2/rst reset input reset input reset input reset input reset input reset input reset input* 4 i/o port* 1 i/o port* 1 - previous state kept - input blocked* 1, * 2 -hi-z - input blocked* 1, * 2 - previous state kept - input blocked* 1, * 2 -hi-z - input blocked* 1, * 2 - hi-z - input enabled* 3 (however, it does not function.) pg1/x0a oscillation input oscillation input hi-z hi-z hi-z hi-z ? i/o port* 1 i/o port* 1 - previous state kept - input blocked* 1, * 2 -hi-z - input blocked* 1, * 2 - previous state kept - input blocked* 1, * 2 -hi-z - input blocked* 1, * 2 - hi-z - input enabled* 3 (however, it does not function.) pg2/x1a oscillation input oscillation input hi-z hi-z hi-z hi-z ? i/o port* 1 i/o port* 1 - previous state kept - input blocked* 1, * 2 -hi-z - input blocked* 1, * 2 - previous state kept - input blocked* 1, * 2 -hi-z - input blocked* 1, * 2 - hi-z - input enabled* 3 (however, it does not function.) p00/an00 i/o port/ peripheral function i/o/ analog input i/o port/ peripheral function i/o/ analog input - previous state kept - input blocked* 2, * 5 -hi-z* 6 - input blocked* 2, * 5 - previous state kept - input blocked* 2, * 5 -hi-z* 6 - input blocked* 2, * 5 - hi-z - input blocked* 2 p01/an01 p02/int02/ an02/sck p03/int03/ an03/sot p04/int04/ an04/sin/ ec0 p05/int05/ an05/to00
document number: 002-04696 rev. *a page 55 of 105 mb95650l series spl: pin state setting bit in the standby control register (stbc:spl) hi-z: high impedance *1: the pin stays at the state shown when configured as a general-purpose i/o port. *2: ?input blocked? means direct input gate operation from the pin is disabled. *3: ?input enabled? means that the input fu nction is enabled. while the input function is enabled, perform a pull-up or pull-dow n operation in order to prevent leaks due to external input. if a pin is used as an output port, it s pin state is the same as tha t of other ports. *4: the pf2/rst pin stays at the state shown when configured as a reset pin. *5: though input is blocked, an external interrupt can be input when the external interrupt request is enabled. *6: the pull-up control se tting is still effective. *7: the i 2 c bus interface can wake up the mcu in stop mode or watch mode when its mcu standby mode wakeup function is enabled. for details of the mcu standby mode wakeup function, refer to ?chapter 19 i 2 c bus interface? in ?new 8fx mb95650l series hardware manual?. p06/int06/ to01 i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 2, * 5 -hi-z* 6 - input blocked* 2, * 5 - previous state kept - input blocked* 2, * 5 -hi-z* 6 - input blocked* 2, * 5 - hi-z - input blocked* 2 p07/int07/ to10 p14/sda0 i/o port/ peripheral func- tion i/o i/o port/ peripheral func- tion i/o - previous state kept - input blocked* 2, * 7 -hi-z - input blocked* 2, * 7 - previous state kept - input blocked* 2, * 7 -hi-z - input blocked* 2, * 7 - hi-z - input enabled* 3 (however, it does not function.) p15/scl0 p16/sda1/ uo0 p17/scl1/ ui0 p12/dbg/ ec0 i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 2 -hi-z - input blocked* 2 - previous state kept - input blocked* 2 -hi-z - input blocked* 2 - hi-z - input enabled* 3 (however, it does not function.) p62/to10/ uck0 p63/to11 p64/ec1 pin name normal operation sleep mode stop mode watch mode on reset spl=0 spl=1 spl=0 spl=1
document number: 002-04696 rev. *a page 56 of 105 mb95650l series 18. electrical characteristics 18.1 absolute maximum ratings *1: these parameters are based on the condition that v ss is 0.0 v. *2: v 1 and v 0 must not exceed v cc ? 0.3 v. v 1 must not exceed the rated voltage. however, if the maximum current to/from an input is limited by means of an external component, the i clamp rating is used instead of the v i rating. (continued) parameter symbol rating unit remarks min max power supply voltage* 1 v cc v ss ?? 0.3 v ss ? 6v input voltage* 1 v i v ss ?? 0.3 v ss ? 6v*2 output voltage* 1 v o v ss ?? 0.3 v ss ? 6v*2 maximum clamp current i clamp ? 2 ? 2 ma applicable to specific pins* 3 total maximum clamp current ? |i clamp | ? 20 ma applicable to specific pins* 3 ?l? level maximum output current i ol ?15ma ?l? level average current i olav1 ? 4 ma other than p05 to p07, p62 and p63 average output current = operating current ? operating ratio (1 pin) i olav2 12 p05 to p07, p62 and p63 average output current = operating current ? operating ratio (1 pin) ?l? level total maximum output current ? i ol ?100ma ?l? level total average output current ? i olav ?37ma total average output current = operating current ? operating ratio (total number of pins) ?h? level maximum output current i oh ? ? 15 ma ?h? level average current i ohav1 ? ? 4 ma other than p05 to p07, p62 and p63 average output current = operating current ? operating ratio (1 pin) i ohav2 ? 8 p05 to p07, p62 and p63 average output current = operating current ? operating ratio (1 pin) ?h? level total maximum output current ? i oh ? ? 100 ma ?h? level total average output current ? i ohav ? ? 47 ma total average output current = operating current ? operating ratio (total number of pins) power consumption p d ?320mw operating temperature t a ? 40 ? 85 ? c storage temperature t stg ? 55 ? 150 ? c
document number: 002-04696 rev. *a page 57 of 105 mb95650l series (continued) *3: specific pins: p00 to p07, p14, p 15, p62 to p64, pf 0, pf1, pg1, pg2 ? use under recommended operating conditions. ? use with dc voltage (current). ? the hv (high voltage) signal is an input signal exceeding the v cc voltage. always connect a limiting resistor between the hv (high voltage) signal and the microcontroller before applying the hv (high voltage) signal. ? the value of the limiting resistor should be set to a valu e at which the current to be input to the microcontroller pin when the hv (high voltage) signal is input is below the stan dard value, irrespective of wh ether the current is transient current or stationary current. ? when the microcontroller drive current is low, such as in low power consumption mo des, the hv (high voltage) input potential may pass through the protective diode to increase the potential of the v cc pin, affecting other devices. ? if the hv (high voltage) signal is input when the microcon troller power supply is off (not fixed at 0 v), since power is supplied from the pins, incomplete operations may be executed. ? if the hv (high voltage) input is input after power-on, since power is supplied from the pins, the voltage of power supply may not be sufficient to enable a power-on reset. ? do not leave the hv (high voltage) input pin unconnected. ? example of a recommended circuit: warning: semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. do not exceed any of these ratings. hv(high voltage) input (0 v to 16 v) protective diode v cc n-ch p-ch r limiting resistor input/output equivalent circuit
document number: 002-04696 rev. *a page 58 of 105 mb95650l series 18.2 recommended operating conditions (v ss = 0.0 v) *1: the minimum power supply voltage becomes 2.18 v when a product with the low-voltage detection reset is used or when the on-chip debug mode is used. *2: use a ceramic capacitor or a capacitor with equivalent freque ncy characteristics. for the connection to a decoupling capacit or c s , see the diagram below. to prevent the device from unintentional ly entering an unknown mode due to noise, minimize the distance between the c pin and c s and the distance between c s and the v ss pin when designing the layout of a printed circuit board. warning: the recommended operating conditi ons are required in order to ensure th e normal operation of the semiconductor device. all of the device 's electrical characteristics are warranted when the device is operated under these conditions. any use of semiconductor devices will be under their recommended operating condition. operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. no warranty is made with respect to any use, operating condit ions or combinations not repr esented on this data sheet. if you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. parameter symbol value unit remarks min max power supply voltage v cc 1.8* 1 5.5 v in normal operation decoupling capacitor c s 0.2 10 f a capacitor of about 1.0 f is recommended. * 2 operating temperature t a ? 40 ? 85 ? c other than on-chip debug mode ? 5 ? 35 on-chip debug mode c cs dbg * rst dbg / rst / c pins connection diagram *: connect the dbg pin to an external pull-up resistor of 2 k ? or above. after power-on, ensure that the dbg pin does not stay at ?l? level until the reset output is re leased. the dbg pin becomes a communication pin in debug mode. since the actual pull-up resistance depends on the tool used and the interconnection length, refer to the tool document when selecting a pull-up resistor.
document number: 002-04696 rev. *a page 59 of 105 mb95650l series 18.3 dc characteristics (v cc = 3.0 v ? 10%, v ss = 0.0 v, t a = ? 40 c to ? 85 c) (continued) parameter symbol pin name condition value unit remarks min typ max ?h? level input voltage v ihi1 p04, p16, p17 *1 0.7 v cc ?v cc ? 0.3 v cmos input level v ihi2 p14, p15 *1 0.7 v cc ?v cc ? 5.5 v cmos input level v ihs p00 to p03, p05 to p07, p12, p62 to p64, pf0, pf1, pg1, pg2 *1 0.8 v cc ?v cc ? 0.3 v hysteresis input v ihm pf2 ? 0.8 v cc ?v cc ? 0.3 v hysteresis input ?l? level input voltage v ili p04, p14 to p17 *1 v ss ?? 0.3 ? 0.3 v cc v cmos input level v ils p00 to p03, p05 to p07, p12, p62 to p64, pf0, pf1, pg1, pg2 *1 v ss ?? 0.3 ? 0.2 v cc v hysteresis input v ilm pf2 ? v ss ?? 0.3 ? 0.2 v cc v hysteresis input open-drain output application voltage v d1 p12, pf2 ? v ss ?? 0.3 ? v ss ? 5.5 v v d2 p14, p15 ? v ss ?? 0.3 ? v ss ? 5.5 v v d3 p16, p17 ? v ss ?? 0.3 ? v ss ? 5.5 v in i 2 c mode ?h? level output voltage v oh1 output pins other than p05 to p07, p12, p62, p63 i oh = ? 4 ma* 2 v cc ?? 0.5 ? ? v v oh2 p05 to p07, p62, p63 i oh = ? 8 ma* 3 v cc ?? 0.5 ? ? v ?l? level output voltage v ol1 output pins other than p05 to p07, p62, p63 i ol = 4 ma* 4 ??0.4v v ol2 p05 to p07, p62, p63 i ol = 12 ma* 5 ??0.4v input leak current (hi-z output leak current) i li all input pins 0.0 v < v i < v cc ? 5? ? 5a when the internal pull-up resistor is disabled internal pull-up resistor r pull p00 to p07, p62 to p64, pg1, pg2 v i = 0 v 75 100 150 k ? when the internal pull-up resistor is enabled input capacitance c in other than v cc and v ss f = 1 mhz ? 5 15 pf
document number: 002-04696 rev. *a page 60 of 105 mb95650l series (v cc = 3.0 v ? 10%, v ss = 0.0 v, t a = ? 40 c to ? 85 c) (continued) parameter symbol pin name condition value unit remarks min typ* 1 max* 6 power supply current* 7 i cc v cc (external clock operation) f ch = 32 mhz f mp = 16 mhz main clock mode (divided by 2) ?4.26.8ma except during flash memory programming and erasing ?9.314.7ma during flash memory programming and erasing ? 6 10 ma at a/d conversion i ccs f ch = 32 mhz f mp = 16 mhz main sleep mode (divided by 2) ?1.7 3ma i ccl f cl = 32 khz f mpl = 16 khz subclock mode (divided by 2) t a = ? 25 c ?3560a i ccls f cl = 32 khz f mpl = 16 khz subsleep mode (divided by 2) t a = ? 25 c ?2 7a i cct f cl = 32 khz watch mode main stop mode t a = ? 25 c ?1 6 a i ccmcrpll v cc f mcrpll = 16 mhz f mp = 16 mhz main cr pll clock mode (multiplied by 4) ?4.37.7ma i ccmpll f mpll = 16 mhz f mp = 16 mhz main pll clock mode (multiplied by 4) ?4.1 7ma i ccmcr f crh = 4 mhz f mp = 4 mhz main cr clock mode ?1.5 3ma i ccscr sub-cr clock mode (divided by 2) t a = ? 25 c ? 50 100 a
document number: 002-04696 rev. *a page 61 of 105 mb95650l series (v cc = 3.0 v ? 10%, v ss = 0.0 v, t a = ? 40 c to ? 85 c) *1: v cc = 3.0 v, t a = ? 25 c *2: when v cc is smaller than 4.5 v, the condition becomes i oh = ? 2 ma. *3: when v cc is smaller than 4.5 v, the condition becomes i oh = ? 4 ma. *4: when v cc is smaller than 4.5 v, the condition becomes i ol = 2 ma. *5: when v cc is smaller than 4.5 v, the condition becomes i oh = 6 ma. *6: v cc = 3.3 v, t a = ? 85 c (unless otherwise specified) *7: ? the power supply current is determined by the external clo ck. when the low-voltage detectio n reset circuit is selected, the power supply current is the sum of adding the current cons umption of the low-voltage detection reset circuit (i plvd ) to one of the values from i cc to i cch . in addition, when the low-voltage detection reset circui t and a cr oscillator are selected, the power supply current is the sum of adding up the current consum ption of the low-voltage detection reset circuit (i plvd ), the current consumption of the cr oscillator (i crh or i crl ) and one of the values from i cc to i cch . in on-chip debug mode, the main cr oscillator (i crh ) and the low-voltage detection reset circuit are always in operation, and current cons umption therefore increases accordingly. ? see ?18.4. ac characteristics 18.4.1. clock timing? for f ch , f cl , f crh , f mcrpll and f mpll . ? see ?18.4. ac characteristics 18.4. 2. source clock/machine clock? for f mp and f mpl . ? the power supply current in subclock mode is determined by the external clock. in s ubclock mode, current consumption in using the crystal oscillator is higher than that in using the external clock. when the cr ystal oscillator is used, the power supply c urrent is the sum of adding i sosc (current consumption of the suboscillator) to the power supply current in using the external clock. for details of controlling the subclock, refer to ?chapter 3 clock controller? and ?chapter 24 system configuration register? i n ?new 8fx mb95650l series hardware manual?. parameter symbol pin name condition value unit remarks min typ* 1 max* 6 power supply current* 7 i ccts v cc (external clock operation) f ch = 32 mhz time-base timer mode t a = ? 25 c ? 450 500 a i cch substop mode t a = ? 25 c ?0.7 5 a i plvd v cc current consumption of the low-voltage detection reset circuit in operation ?626a i ilvd current consumption of the low-voltage detection interrupt circuit operating in normal mode ?614a i ilvdl current consumption of the low-voltage detection interrupt circuit operating in low power consumption mode ?310a i crh current consumption of the main cr oscillator ? 270 320 a i crl current consumption of the sub-cr oscillator oscillating at 100 khz ?520a i sosc current consumption of the suboscillator ?0.8 7 a
document number: 002-04696 rev. *a page 62 of 105 mb95650l series 18.4 ac characteristics 18.4.1 clock timing (v cc = 1.8 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to ? 85 c) (continued) parameter symbol pin name condition value unit remarks min typ max clock frequency f ch x0, x1 ? 1 ? 16.25 mhz when the main oscillation circuit is used x0 ? 1 ? 32.5 mhz when the main external clock is used x0, x1 ? ? 4 ? mhz when the main pll clock is used f crh ?? 3.92 4 4.08 mhz operating conditions ? the main cr clock is used. ?0 ?? c ?? t a ??? 70 ?? c 3.8 4 4.2 mhz operating conditions ? the main cr clock is used. ? ? 40 ?? c ? t a ? 0 ?? c, ? 70 ?? c ? t a ? ? 85 ?? c f mcrpll ?? 7.84 8 8.16 mhz operating conditions ? pll multiplication rate: 2 ?0 ?? c ?? t a ??? 70 ?? c 7.6 8 8.4 mhz operating conditions ? pll multiplication rate: 2 ? ? 40 ?? c ? t a ? 0 ?? c, ? 70 ?? c ? t a ? ? 85 ?? c 9.8 10 10.2 mhz operating conditions ? pll multiplication rate: 2.5 ?0 ?? c ?? t a ??? 70 ?? c 9.5 10 10.5 mhz operating conditions ? pll multiplication rate: 2.5 ? ? 40 ?? c ? t a ? 0 ?? c, ? 70 ?? c ? t a ? ? 85 ?? c 11.76 12 12.24 mhz operating conditions ? pll multiplication rate: 3 ?0 ?? c ?? t a ??? 70 ?? c 11.4 12 12.6 mhz operating conditions ? pll multiplication rate: 3 ? ? 40 ?? c ? t a ? 0 ?? c, ? 70 ?? c ? t a ? ? 85 ?? c 15.68 16 16.32 mhz operating conditions ? pll multiplication rate: 4 ?0 ?? c ?? t a ??? 70 ?? c 15.2 16 16.8 mhz operating conditions ? pll multiplication rate: 4 ? ? 40 ?? c ? t a ? 0 ?? c, ? 70 ?? c ? t a ? ? 85 ?? c f mpll ? ? 8 ? 16 mhz when the main pll clock is used
document number: 002-04696 rev. *a page 63 of 105 mb95650l series (continued) (v cc = 1.8 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to ? 85 c) parameter symbol pin name condition value unit remarks min typ max clock frequency f cl x0a, x1a ? ? 32.768 ? khz when the suboscillation circuit is used ? 32.768 ? khz when the sub-external clock is used f crl ? ? 50 100 150 khz when the sub-cr clock is used clock cycle time t hcyl x0, x1 ? 61.5 ? 1000 ns when the main oscillation circuit is used x0 ? 30.8 ? 1000 ns when an external clock is used x0, x1 ? ? 250 ? ns when the main pll clock is used t lcyl x0a, x1a ? ? 30.5 ? s when the subclock is used input clock pulse width t wh1 , t wl1 x0 ? 12.4 ? ? ns when an external clock is used, the duty ratio should range between 40% and 60%. x0, x1 ? ? 125 ? ns when the main pll clock is used t wh2 , t wl2 x0a ? ? 15.2 ? s when an external clock is used, the duty ratio should range between 40% and 60%. input clock rising time and falling time t cr , t cf x0, x0a ? ? ? 5 ns when an external clock is used cr oscillation start time t crhwk ? ? ? ? 50 s when the main cr clock is used t crlwk ? ? ? ? 30 s when the sub-cr clock is used pll oscillation start time t mcrpllwk ????100s when the main cr pll clock is used
document number: 002-04696 rev. *a page 64 of 105 mb95650l series x0, x1 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc t wh1 t wl1 0.2 v cc t hcyl t cr t cf input waveform generated when an external clock (main clock) is used x0 x1 f ch x0 f ch when an external clock is used when a crystal oscillator or a ceramic oscillator is used figure of main clock input port external connection x0a 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc t wh2 t wl2 0.2 v cc t lcyl t cr t cf input waveform generated when an external clock (subclock) is used when a crystal oscillator or a ceramic oscillator is used when an external clock is used x0a x1a x0a f cl f cl figure of subclock input port external connection
document number: 002-04696 rev. *a page 65 of 105 mb95650l series t crhwk 1/f crh main cr clock oscillation starts oscillation stabilizes input waveform generated when an internal clock (main cr clock) is used t crlwk 1/f crl sub-cr clock oscillation starts oscillation stabilizes input waveform generated when an internal clock (sub-cr clock) is used t mcrpllwk 1/f mcrpll main cr pll clock oscillation starts oscillation stabilizes input waveform generated when an intern al clock (main cr pll clock) is used
document number: 002-04696 rev. *a page 66 of 105 mb95650l series 18.4.2 source clock/machine clock (v cc = 1.8 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to ? 85 c) (continued) parameter symbol pin name value unit remarks min typ max source clock cycle time* 1 t sclk ? 61.5 ? 2000 ns when the main external clock is used min: f ch = 32.5 mhz, divided by 2 max: f ch = 1 mhz, divided by 2 ? 250 ? ns when the main cr clock is used 62.5 ? 250 ns when the main pll clock is used min: f ch = 4 mhz, multiplied by 4 max: f ch = 4 mhz, no division 62.5 ? 250 ns when the main cr pll clock is used min: f crh = 4 mhz, multiplied by 4 max: f crh = 4 mhz, no division ?61?s when the suboscillation clock is used f cl = 32.768 khz, divided by 2 ?20?s when the sub-cr clock is used f crl = 100 khz, divided by 2 source clock frequency f sp ? 0.5 ? 16.25 mhz when the main oscillation clock is used ? 4 ? mhz when the main cr clock is used 4 ? 16 mhz when the main pll clock is used 4 ? 16 mhz when the main cr pll clock is used f spl ? 16.384 ? khz when the suboscillation clock is used ? 50 ? khz when the sub-cr clock is used f crl = 100 khz, divided by 2 machine clock cycle time* 2 (minimum instruction execution time) t mclk ? 61.5 ? 32000 ns when the main oscillation clock is used min: f sp = 16.25 mhz, no division max: f sp = 0.5 mhz, divided by 16 250 ? 4000 ns when the main cr clock is used min: f sp = 4 mhz, no division max: f sp = 4 mhz, divided by 16 62.5 ? 4000 ns when the main pll clock is used min: f sp = 4 mhz, multiplied by 4 max: f sp = 4 mhz, divided by 16 62.5 ? 4000 ns when the main cr pll clock is used min: f sp = 4 mhz, multiplied by 4 max: f sp = 4 mhz, divided by 16 61 ? 976.5 s when the suboscillation clock is used min: f spl = 16.384 khz, no division max: f spl = 16.384 khz, divided by 16 20 ? 320 s when the sub-cr clock is used min: f spl = 50 khz, no division max: f spl = 50 khz, divided by 16
document number: 002-04696 rev. *a page 67 of 105 mb95650l series (continued) (v cc = 1.8 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to ? 85 c) *1: this is the clock before it is divided according to the division ratio set by the machine clock division ratio select bits (sycc:div[1:0]). this source clock is divided to become a machin e clock according to the division ratio set by the machine cloc k division ratio select bits (sycc:di v[1:0]). in addition, a source clock can be selected from the following. ? main clock divided by 2 ? pll multiplication of main clock (select a multiplication rate from 2, 2.5, 3 and 4.) ? main cr clock ? pll multiplication of main cr clock (select a multiplication rate from 2, 2.5, 3 and 4.) ? subclock divided by 2 ? sub-cr clock divided by 2 *2: this is the operating clock of the microcontroller. a machine clock can be selected from the following. ? source clock (no division) ? source clock divided by 4 ? source clock divided by 8 ? source clock divided by 16 parameter symbol pin name value unit remarks min typ max machine clock frequency f mp ? 0.031 ? 16.25 mhz when the main oscillation clock is used 0.25 ? 4 mhz when the main cr clock is used 0.25 ? 16 mhz when the main pll clock is used 0.25 ? 16 mhz when the main cr pll clock is used f mpl 1.024 ? 16.384 khz when the suboscillation clock is used 3.125 ? 50 khz when the sub-cr clock is used f crl = 100 khz
document number: 002-04696 rev. *a page 68 of 105 mb95650l series f ch (main oscillation clock) divided by 2 divided by 2 divided by 2 f crh (main cr clock) f mcrpll (main cr pll clock) f cl (suboscillation clock) f crl (sub-cr clock) f mpll (main pll clock) sclk (source clock) mclk (machine clock) machine clock divide ratio select bits (sycc:div[1:0]) clock mode select bits (sycc:scs[2:0]) division circuit 1 1/4 1/8 1/16 schematic diagram of the clock generation block operating voltage (v) a/d converter operation range 5.5 3 mhz 16 khz 10 mhz 16.25 mhz source clock frequency (f sp /f spl ) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.8 1.5 0.0 operating voltage - operating frequency (t a = ? 40 c to ? 85 c)
document number: 002-04696 rev. *a page 69 of 105 mb95650l series 18.4.3 external reset (v cc = 3.0 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to ? 85 c) *: see ?18.4.2. source cl ock/machine clock? for t mclk . parameter symbol value unit remarks min max rst ?l? level pulse width t rstl 2 t mclk * ? ns 0.2 v cc rst 0.2 v cc t rstl
document number: 002-04696 rev. *a page 70 of 105 mb95650l series 18.4.4 power-on reset (v ss = 0.0 v, t a = ? 40 c to ? 85 c) parameter symbol pin name value unit remarks min typ max power supply rising time dv/dt v cc 0.1 ? ? v/ms power supply cutoff time t off 1??ms reset release voltage v deth 1.44 1.60 1.76 v at voltage rise reset detection voltage v detl 1.39 1.55 1.71 v at voltage fall reset release delay time t ond ? ? 10 ms dv/dt ? 0.1 mv/s reset detection delay time t offd ??0.4msdv/dt ? ? 0.04 mv/s v deth v cc power-on reset v detl 0.2 v t off t offd t ond dv dt 0.2 v
document number: 002-04696 rev. *a page 71 of 105 mb95650l series 18.4.5 peripheral input timing (v cc = 3.0 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to ? 85 c) *: see ?18.4.2. source cl ock/machine clock? for t mclk . parameter symbol pin name value unit min max peripheral input ?h? pulse width t ilih int02 to int07, ec0, ec1 2 t mclk * ? ns peripheral input ?l? pulse width t ihil 2 t mclk * ? ns int02 to int07, ec0, ec1 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t ilih t ihil
document number: 002-04696 rev. *a page 72 of 105 mb95650l series 18.4.6 lin-uart timing sampling is executed at the rising edge of the sampling clock* 1 , and serial clock delay is disabled* 2 . (escr register : sces bit = 0, eccr register : scde bit = 0) (v cc = 3.0 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to ? 85 c) *1: there is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. *2: the serial clock delay function is a function used to delay the output signal of the serial clock for half the clock. *3: see ?18.4.2. source cl ock/machine clock? for t mclk . parameter symbol pin name condition value unit min max serial clock cycle time t scyc sck internal clock operation output pin: c l = 80 pf ? 1 ttl 5 t mclk * 3 ?ns sck ? ? sot delay time t slovi sck, sot ? 50 ? 50 ns valid sin ? sck ? t ivshi sck, sin t mclk * 3 ? 80 ? ns sck ? ? valid sin hold time t shixi sck, sin 0 ? ns serial clock ?l? pulse width t slsh sck external clock operation output pin: c l = 80 pf ? 1 ttl 3 t mclk * 3 ? t r ?ns serial clock ?h? pulse width t shsl sck t mclk * 3 ? 10 ? ns sck ? ? sot delay time t slove sck, sot ? 2 t mclk * 3 ? 60 ns valid sin ? sck ? t ivshe sck, sin 30 ? ns sck ? ? valid sin hold time t shixe sck, sin t mclk * 3 ? 30 ? ns sck fall time t f sck ? 10 ns sck rise time t r sck ? 10 ns
document number: 002-04696 rev. *a page 73 of 105 mb95650l series 0.2 v cc 0.2 v cc 0.8 v cc t slovi t ivshi t shixi 0.8 v cc 0.2 v cc sck sot sin 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc t scyc internal shift clock mode 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc t slove t ivshe t shixe 0.8 v cc 0.2 v cc sck sot sin 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc t slsh t shsl t r 0.8 v cc t f external shift clock mode
document number: 002-04696 rev. *a page 74 of 105 mb95650l series sampling is executed at the falling edge of the sampling clock* 1 , and serial clock delay is disabled* 2 . (escr register : sces bit = 1, eccr register : scde bit = 0) (v cc = 3.0 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to ? 85 c) *1: there is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. *2: the serial clock delay function is a function used to delay the output signal of the serial clock for half the clock. *3: see ?18.4.2. source cl ock/machine clock? for t mclk . parameter symbol pin name condition value unit min max serial clock cycle time t scyc sck internal clock operation output pin: c l = 80 pf ? 1 ttl 5 t mclk * 3 ?ns sck ? ? sot delay time t shovi sck, sot ? 50 ? 50 ns valid sin ? sck ? t ivsli sck, sin t mclk * 3 ? 80 ? ns sck ?? valid sin hold time t slixi sck, sin 0 ? ns serial clock ?h? pulse width t shsl sck external clock operation output pin: c l = 80 pf ? 1 ttl 3 t mclk * 3 ?? t r ?ns serial clock ?l? pulse width t slsh sck t mclk * 3 ? 10 ? ns sck ? ? sot delay time t shove sck, sot ? 2 t mclk * 3 ? 60 ns valid sin ? sck ? t ivsle sck, sin 30 ? ns sck ?? valid sin hold time t slixe sck, sin t mclk * 3 ? 30 ? ns sck fall time t f sck ? 10 ns sck rise time t r sck ? 10 ns
document number: 002-04696 rev. *a page 75 of 105 mb95650l series 0.2 v cc 0.8 v cc 0.8 v cc t shovi t ivsli t slixi 0.8 v cc 0.2 v cc sck sot sin 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc t scyc internal shift clock mode 0.2 v cc 0.2 v cc 0.2 v cc 0.8 v cc t shove t ivsle t slixe 0.8 v cc 0.2 v cc sck sot sin 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc t shsl t slsh t f 0.8 v cc t r external shift clock mode
document number: 002-04696 rev. *a page 76 of 105 mb95650l series sampling is executed at the rising edge of the sampling clock* 1 , and serial clock delay is enabled* 2 . (escr register : sces bit = 0, eccr register : scde bit = 1) (v cc = 3.0 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to ? 85 c) *1: there is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. *2: the serial clock delay function is a function used to delay the output signal of the serial clock for half the clock. *3: see ?18.4.2. source cl ock/machine clock? for t mclk . parameter symbol pin name condition value unit min max serial clock cycle time t scyc sck internal clock operation output pin: c l = 80 pf ? 1 ttl 5 t mclk * 3 ?ns sck ??? sot delay time t shovi sck, sot ? 50 ? 50 ns valid sin ? sck ? t ivsli sck, sin t mclk * 3 ? 80 ? ns sck ?? valid sin hold time t slixi sck, sin 0 ? ns sot ? sck ? delay time t sovli sck, sot 3t mclk * 3 ?? 70 ? ns 0.8 v cc 0.2 v cc 0.2 v cc t shovi t sovli t ivsli t slixi 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc sck sot sin 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc t scyc
document number: 002-04696 rev. *a page 77 of 105 mb95650l series sampling is executed at the falling edge of the sampling clock* 1 , and serial clock delay is enabled* 2 . (escr register : sces bit = 1, eccr register : scde bit = 1) (v cc = 3.0 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to ? 85 c) *1: there is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. *2: the serial clock delay function is a function used to delay the output signal of the serial clock for half the clock. *3: see ?18.4.2. source cl ock/machine clock? for t mclk . parameter symbol pin name condition value unit min max serial clock cycle time t scyc sck internal clock operation output pin: c l = 80 pf ? 1 ttl 5 t mclk * 3 ?ns sck ? ? sot delay time t slovi sck, sot ? 50 ? 50 ns valid sin ? sck ? t ivshi sck, sin t mclk * 3 ? 80 ? ns sck ? ? valid sin hold time t shixi sck, sin 0 ? ns sot ? sck ? delay time t sovhi sck, sot 3t mclk * 3 ?? 70 ? ns 0.2 v cc 0.8 v cc 0.8 v cc t slovi t sovhi t ivshi t shixi 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc sck sot sin 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc t scyc
document number: 002-04696 rev. *a page 78 of 105 mb95650l series 18.4.7 low-vo ltage detection normal mode (v cc = 1.8 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to ? 85 c) parameter symbol value unit remarks min typ max reset release voltage v pdl ? 1.88 2.03 2.18 v at power supply rise reset detection voltage v pdl ? 1.8 1.93 2.06 v at power supply fall interrupt release voltage 0 v idl0 ? 2.13 2.3 2.47 v at power supply rise interrupt detection voltage 0 v idl0 ? 2.05 2.2 2.35 v at power supply fall interrupt release voltage 1 v idl1 ? 2.41 2.6 2.79 v at power supply rise interrupt detection voltage 1 v idl1 ? 2.33 2.5 2.67 v at power supply fall interrupt release voltage 2 v idl2 ? 2.69 2.9 3.11 v at power supply rise interrupt detection voltage 2 v idl2 ? 2.61 2.8 2.99 v at power supply fall interrupt release voltage 3 v idl3 ? 3.06 3.3 3.54 v at power supply rise interrupt detection voltage 3 v idl3 ? 2.98 3.2 3.42 v at power supply fall interrupt release voltage 4 v idl4 ? 3.43 3.7 3.97 v at power supply rise interrupt detection voltage 4 v idl4 ? 3.35 3.6 3.85 v at power supply fall interrupt release voltage 5 v idl5 ? 3.81 4.1 4.39 v at power supply rise interrupt detection voltage 5 v idl5 ? 3.73 4 4.27 v at power supply fall power supply start voltage v off ??1.6v power supply end voltage v on 4.39 ? ? v power supply voltage change time (at power supply rise) t r 697.5 ? ? s slope of power supply that the reset release signal generates within the rating (v pdl ? /v idl ? ) power supply voltage change time (at power supply fall) t f 697.5 ? ? s slope of power supply that the reset release signal generates within the rating (v pdl ? /v idl ? ) reset release delay time t dp1 ? ? 30 s reset detection delay time t dp2 ? ? 30 s interrupt release delay time t di1 ? ? 30 s interrupt detection delay time t di2 ? ? 30 s lvd reset threshold voltage transition stabilization time t stb ? ? 30 s
document number: 002-04696 rev. *a page 79 of 105 mb95650l series low power consumption mode (v cc = 1.8 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to ? 85 c) note: when used for interrupt, the low-voltage detection circ uit can be switched between the normal mode and the low power consumption mode. compared with the normal mode, while th e low power consumption mode has lower detection voltage accuracy and lower release voltage accuracy, it has the lower power consumption. see ?18.3 dc characteristics? for the difference in current consumption between the normal mode and the low power consumption mode. for details of the method for switching between the normal mode and the low power cons umption mode, refer to ?chapter 17 low-voltage detection circuit? in ?new 8fx mb95650l series hardware manual?. parameter symbol value unit remarks min typ max interrupt release voltage 0 v idll0 ? 2.06 2.3 2.54 v at power supply rise interrupt detection voltage 0 v idll0 ? 1.98 2.2 2.42 v at power supply fall interrupt release voltage 1 v idll1 ? 2.33 2.6 2.87 v at power supply rise interrupt detection voltage 1 v idll1 ? 2.25 2.5 2.75 v at power supply fall interrupt release voltage 2 v idll2 ? 2.6 2.9 3.2 v at power supply rise interrupt detection voltage 2 v idll2 ? 2.52 2.8 3.08 v at power supply fall interrupt release voltage 3 v idll3 ? 2.96 3.3 3.64 v at power supply rise interrupt detection voltage 3 v idll3 ? 2.88 3.2 3.52 v at power supply fall interrupt release voltage 4 v idll4 ? 3.32 3.7 4.08 v at power supply rise interrupt detection voltage 4 v idll4 ? 3.24 3.6 3.96 v at power supply fall interrupt release voltage 5 v idll5 ? 3.68 4.1 4.52 v at power supply rise interrupt detection voltage 5 v idll5 ? 3.6 4 4.4 v at power supply fall power supply start voltage v offl ??1.6v power supply end voltage v onl 4.52 ? ? v power supply voltage change time (at power supply rise) t rl 7300 ? ? s slope of power supply that the interrupt release signal generates within the rating (v idll ? ) power supply voltage change time (at power supply fall) t fl 7300 ? ? s slope of power supply that the interrupt detection signal generates within the rating (v idll ? ) interrupt release delay time t dil1 ??400s interrupt detection delay time t dil2 ??400s interrupt threshold voltage transition stabilization time t stbl ??400s interrupt low-voltage detection mode switch time t mdsw ??400s normal mode ? low power consumption mode
document number: 002-04696 rev. *a page 80 of 105 mb95650l series t dp2 /t di2 /t dil2 t dp1 /t di1 /t dil1 t r /t rl t f /t fl v cc v on /v onl v off /v offl v pdl + /v idl + v pdl ? /v idl ? time time internal reset signal or interrupt signal
document number: 002-04696 rev. *a page 81 of 105 mb95650l series 18.4.8 i 2 c bus interface timing (v cc = 3.0 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to ? 85 c) *1: r represents the pull-up resistor of the scl0/1 and sda0/1 li nes, and c the load capacitor of the scl0/1 and sda0/1 lines. *2: the maximum t hd;dat in the standard-mode is applicable only when the time during which the device is holding the scl signal at ?l? (t low ) does not extend. *3: a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, provided that the condition of t su;dat ? 250 ns is fulfilled. parameter symbol pin name condition value unit standard-mode fast-mode min max min max scl clock frequency f scl scl0, scl1 r = 1.7 k ? , c = 50 pf* 1 0 100 0 400 khz (repeated) start condition hold time sda ??? scl ? t hd;sta scl0, scl1, sda0, sda1 4.0 ? 0.6 ? s scl clock ?l? width t low scl0, scl1 4.7 ? 1.3 ? s scl clock ?h? width t high scl0, scl1 4.0 ? 0.6 ? s (repeated) start condition setup time scl ??? sda ? t su;sta scl0, scl1, sda0, sda1 4.7 ? 0.6 ? s data hold time scl ??? sda ?? t hd;dat scl0, scl1, sda0, sda1 03.45 *2 00.9 *3 s data setup time sda ???? scl ? t su;dat scl0, scl1, sda0, sda1 0.25 ? 0.1 ? s stop condition setup time scl ? ? sda ? t su;sto scl0, scl1, sda0, sda1 4?0.6?s bus free time between stop condition and start condition t buf scl0, scl1, sda0, sda1 4.7 ? 1.3 ? s sda0, sda1 scl0, scl1 t wakeup t hd;sta t su;dat f scl t hd;sta t su;sta t low t hd;dat t high t su;sto t buf
document number: 002-04696 rev. *a page 82 of 105 mb95650l series (v cc = 3.0 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to ? 85 c) (continued) parameter symbol pin name condition value* 2 unit remarks min max scl clock ?l? width t low scl0, scl1 r = 1.7 k ? , c = 50 pf* 1 (2 ? nm/2)t mclk ? 20 ? ns master mode scl clock ?h? width t high scl0, scl1 (nm/2)t mclk ? 20 (nm/2)t mclk ? 20 ns master mode start condition hold time t hd;sta scl0, scl1, sda0, sda1 (-1 ? nm/2)t mclk ? 20 (-1 ? nm)t mclk ? 20 ns master mode maximum value is applied when m, n = 1, 8. otherwise, the minimum value is applied. stop condition setup time t su;sto scl0, scl1, sda0, sda1 (1 ? nm/2)t mclk ? 20 (1 ? nm/2)t mclk ? 20 ns master mode start condition setup time t su;sta scl0, scl1, sda0, sda1 (1 ? nm/2)t mclk ? 20 (1 ? nm/2)t mclk ? 20 ns master mode bus free time between stop condition and start condition t buf scl0, scl1, sda0, sda1 (2 nm ? 4) t mclk ? 20 ? ns data hold time t hd;dat scl0, scl1, sda0, sda1 3 t mclk ? 20 ? ns master mode
document number: 002-04696 rev. *a page 83 of 105 mb95650l series (v cc = 3.0 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to ? 85 c) (continued) parameter symbol pin name condition value* 2 unit remarks min max data setup time t su;dat scl0, scl1, sda0, sda1 r = 1.7 k ? , c = 50 pf* 1 (-2 ? nm/2) t mclk ? 20 (-1 ? nm/2) t mclk ? 20 ns master mode it is assumed that ?l? of scl is not extended. the minimum value is applied to the first bit of continuous data. otherwise, the maximum value is applied. setup time between clearing interrupt and scl rising t su;int scl0, scl1 (nm/2) t mclk ? 20 (1 ? nm/2) t mclk ? 20 ns the minimum value is applied to the interrupt at the ninth scl ? . the maximum value is applied to the interrupt at the eighth scl ? . scl clock ?l? width t low scl0, scl1 4 t mclk ? 20 ? ns at reception scl clock ?h? width t high scl0, scl1 4 t mclk ? 20 ? ns at reception start condition detection t hd;sta scl0, scl1, sda0, sda1 2 t mclk ? 20 ? ns no start condition is detected when 1t mclk is used at reception. stop condition detection t su;sto scl0, scl1, sda0, sda1 2 t mclk ? 20 ? ns no stop condition is detected when 1t mclk is used at reception. restart condition detection condition t su;sta scl0, scl1, sda0, sda1 2 t mclk ? 20 ? ns no restart condition is detected when 1 t mclk is used at reception.
document number: 002-04696 rev. *a page 84 of 105 mb95650l series (continued) (v cc = 3.0 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to ? 85 c) *1: r represents the pull-up resistor of the scl0/scl1 and sda0/sda1 lines, and c the load capacitor of the scl0/scl1 and sda0/sda1 lines. *2: ? see ?18.4.2. source clock/machine clock? for t mclk . ? m represents the cs[4:3] bits in the i 2 c clock control register ch. 0/ch. 1 (iccr0/iccr1). ? n represents the cs[2:0] bits in the i 2 c clock control register ch. 0/ch. 1 (iccr0/iccr1). ? the actual timing of the i 2 c bus interface is determined by the values of m and n set by the machine clock (t mclk ) and the cs[4:0] bits in the iccr0/iccr1 register. ? standard-mode: m and n can be set to values in the following range: 0.9 mhz ? t mclk (machine clock) ? 16.25 mhz. the usable frequencies of the machine clock are determ ined by the settings of m and n as shown below. (m, n) = (1, 8) : 0.9 mhz < t mclk ? 1 mhz (m, n) = (1, 22), (5, 4), (6, 4), (7, 4), (8, 4) : 0.9 mhz < t mclk ? 2 mhz (m, n) = (1, 38), (5, 8), (6, 8), (7, 8), (8, 8) : 0.9 mhz < t mclk ? 4 mhz (m, n) = (1, 98), (5, 22), (6, 22), (7, 22) : 0.9 mhz < t mclk ? 10 mhz (m, n) = (8, 22) : 0.9 mhz < t mclk ? 16.25 mhz ? fast-mode: m and n can be set to values in the following range: 3.3 mhz < t mclk (machine clock) < 16.25 mhz. the usable frequencies of the machine clock are determ ined by the settings of m and n as shown below. (m, n) = (1, 8) : 3.3 mhz < t mclk ? 4 mhz (m, n) = (1, 22), (5, 4) : 3.3 mhz < t mclk ? 8 mhz (m, n) = (1, 38), (6, 4), (7, 4), (8, 4) : 3.3 mhz < t mclk ? 10 mhz (m, n) = (5, 8) : 3.3 mhz < t mclk ? 16.25 mhz parameter symbol pin name condition value* 2 unit remarks min max bus free time t buf scl0, scl1, sda0, sda1 r = 1.7 k ? , c = 50 pf* 1 2 t mclk ? 20 ? ns at reception data hold time t hd;dat scl0, scl1, sda0, sda1 2 t mclk ? 20 ? ns at slave transmission mode data setup time t su;dat scl0, scl1, sda0, sda1 t low ? 3 t mclk ? 20 ? ns at slave transmission mode data hold time t hd;dat scl0, scl1, sda0, sda1 0 ? ns at reception data setup time t su;dat scl0, scl1, sda0, sda1 t mclk ? 20 ? ns at reception sda ? ? scl ? (with wakeup function in use) t wakeup scl0, scl1, sda0, sda1 oscillation stabilization wait time ? 2 t mclk ? 20 ?ns
document number: 002-04696 rev. *a page 85 of 105 mb95650l series 18.4.9 uart/sio, serial i/o timing (v cc = 3.0 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to ? 85 c) *: see ?18.4.2. source cl ock/machine clock? for t mclk . parameter symbol pin name condition value unit min max serial clock cycle time t scyc uck0 internal clock operation 4 t mclk *? ns uck ??? uo time t slov uck0, uo0 ? 190 ? 190 ns valid ui ? uck ? t ivsh uck0, ui0 2 t mclk *? ns uck ??? valid ui hold time t shix uck0, ui0 2 t mclk *? ns serial clock ?h? pulse width t shsl uck0 external clock operation 4 t mclk *? ns serial clock ?l? pulse width t slsh uck0 4 t mclk *? ns uck ??? uo time t slov uck0, uo0 ? 190 ns valid ui ? uck ? t ivsh uck0, ui0 2 t mclk *? ns uck ??? valid ui hold time t shix uck0, ui0 2 t mclk *? ns 0.2 v cc 0.2 v cc 0.8 v cc t slov t ivsh t shix 0.8 v cc 0.2 v cc uck0 uo0 ui0 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc t scyc internal shift clock mode t slov t ivsh t shix 0.8 v cc 0.2 v cc uck0 uo0 ui0 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc t slsh t shsl external shift clock mode
document number: 002-04696 rev. *a page 86 of 105 mb95650l series 18.5 a/d converter 18.5.1 a/d converter electrical characteristics (v cc = 1.8 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to ? 85 c) *: see ?18.4.2. notes on using a/d converte r? for details of the minimum sampling time. parameter symbol value unit remarks min typ max resolution ? ? ? 12 bit to ta l e r r o r ? 6? ? 6lsbv cc ? 2.7 v ? 10 ? ? 10 lsb v cc ? 2.7 v linearity error ? 3? ? 3lsbv cc ? 2.7 v ? 5? ? 5lsbv cc ? 2.7 v differential linearity error ? 1.9 ? ? 1.9 lsb v cc ? 2.7 v ? 2.9 ? ? 2.9 lsb v cc ? 2.7 v zero transition voltage v 0t v ss ? 6 lsb ? v ss ? 8.2 lsb mv full-scale transition voltage v fst v cc ? 6.2 lsb ? v cc ? 9.2 lsb mv sampling time t s * ? 10 s compare time t cck 0.861 ? 14 s v cc ? 2.7 v 2.8 ? 14 s v cc ? 2.7 v time of transiting to operation enabled state t stt 1??s analog input current i ain ? 0.3 ? ? 0.3 a analog input voltage v ain v ss ?v cc v
document number: 002-04696 rev. *a page 87 of 105 mb95650l series 18.5.2 notes on using a/d converter external impedance of analog input and its sampling time the a/d converter of the mb95650l series has a sample and hold circ uit. if the external impedance is too high to keep sufficien t sampling time, the analog voltage charged to the capacitor of the internal sample and hold circuit is insufficient, adversely a ffecting a/d conversion precision. theref ore, to satisfy the a/d conversion precision st andard, considering the relationship between the external impedance and minimum sampling time, either adjust the register value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum va lue. in addition, if sufficient sampling time cannot be secure d, connect a capacitor of about 0.1 f to the analog input pin. relationship between external impedance and minimum sampling time the sampling required varies according to external impedance. en sure that the following condition is met when setting the sampl ing time. ts : sampling time rin : input resistance of a/d converter cin : input capacitance of a/d converter rext : output impedance of external circuit a/d conversion error as |v cc ? v ss | decreases, the a/d conversion error increases proportionately. note: the values are reference values. 4.5 v v cc 5.5 v 2.7 v v cc < 4.5 v 0.9 k (max) 1.6 k (max) 13 pf (max) v cc rin cin 13 pf (max) 1.8 v v cc < 2.7 v 4.0 k (max) 13 pf (max) comparator analog input pins (an00 to an05) analog signal source rin cin rext analog input equivalent circuit ts rin rext ? cin 9 ? ? + ? ?
document number: 002-04696 rev. *a page 88 of 105 mb95650l series 18.5.3 definitions of a/d converter terms resolution it indicates the level of analog variation t hat can be distinguished by the a/d converter. when the number of bits is 12, analog voltage can be divided into 2 12 = 4096. linearity error (unit: lsb) it indicates how much an actual conversion value deviates from the straight line connecting the zero transition point (?000000000000? ? ? ?000000000001?) of a device to the full-scale transition point (?1111 11111111? ? ? ?111111111110?) of the same device. differential linear error (unit: lsb) it indicates how much the input voltage required to change the output code by 1 lsb deviates from an ideal value. total error (unit: lsb) it indicates the difference between an actual value and a theoreti cal value. the error can be caused by a zero transition error , a full-scale transition errors, a linearity error, a quantum error, or noise. (continued) v fst ideal i/o characteristics 0x001 0x002 0x003 0x004 0xffd 0xffe 0xfff digital output digital output 2 lsb v 0t 1 lsb 0.5 lsb total error analog input analog input 0x001 0x002 0x003 0x004 0xffd 0xffe 0xfff actual conversion characteristic ideal characteristic actual conversion characteristic n v nt : a/d converter digital output value : voltage at which the digital output transits from 0x(n ? 1) to 0xn {1 lsb (n ? 1) + 0.5 lsb} v nt total error of digital output n v nt ? {1 lsb (n ? 1) + 0.5 lsb} 1 lsb lsb = v cc ? v ss 4096 v 1 lsb = v ss v cc v ss v cc
document number: 002-04696 rev. *a page 89 of 105 mb95650l series (continued) zero transition error linearity error full-scale transition error 0x001 0x002 0x003 0x004 0xffd 0xffe 0xfff digital output differential linearity error of digital output n v (n + 1)t ? v nt 1 lsb ? 1 = linearity error of digital output n v nt ? {1 lsb n + v 0t } 1 lsb = digital output analog input 0x001 0x002 0xffc 0xffd 0x003 0xffe 0xfff 0x004 actual conversion characteristic actual conversion characteristic v 0t (measurement value) actual conversion characteristic actual conversion characteristic v fst (measurement value) v ss v cc v ss v cc v ss v cc v ss v cc analog input digital output analog input ideal characteristic {1 lsb n + v 0t } actual conversion characteristic ideal characteristic actual conversion characteristic v 0t (measurement value) v fst (measurement value) v nt differential linearity error 0x(n ? 2) 0x(n ? 1) 0xn 0x(n + 1) digital output analog input actual conversion characteristic ideal characteristic v nt actual conversion characteristic v (n + 1)t n v nt : a/d converter digital output value : voltage at which the digital output transits from 0x(n ? 1) to 0xn v 0t (ideal value) = v ss + 0.5 lsb [v] v fst (ideal value) = v cc ? 2 lsb [v] ideal characteristic
document number: 002-04696 rev. *a page 90 of 105 mb95650l series 18.6 flash memory program/erase characteristics *1: v cc = 5.5 v, t a = ? 25 c, 0 cycle *2: v cc = 1.8 v, t a = ? 85 c, 100000 cycles *3: these values were converted from the result of a technol ogy reliability assessment. (these values were converted from the re sult of a high temperature accelerated test using the a rrhenius equation with the average temperature being ? 85 c.) parameter value unit remarks min typ max sector erase time (2 kbyte sector) ?0.3* 1 1.6* 2 s the time of writing ?0x00? prior to erasure is excluded. sector erase time (32 kbyte sector) ?0.6* 1 3.1* 2 s the time of writing ?0x00? prior to erasure is excluded. byte writing time ? 17 272 s system-level overhead is excluded. program/erase cycle 100000 ? ? cycle power supply voltage at program/erase 1.8 ? 5.5 v flash memory data retention time 20* 3 ?? year average t a = ? 85 c number of program/erase cycles: 1000 or below 10* 3 ?? average t a = ? 85 c number of program/erase cycl es: 1001 to 10000 inclusive 5* 3 ?? average t a = ? 85 c number of program/erase cycles: 10001 or above
document number: 002-04696 rev. *a page 91 of 105 mb95650l series 19. sample characteristics power supply current temperature characteristics (continued) 0 2 6 4 10 8 1234567 i cc [ma] v cc [v] f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz i cc ? v cc t a ? ? 25 ? c, f mp ? 2, 4, 8, 10, 16 mhz (divided by 2) main clock mode with the external clock operating 0 2 6 4 10 8 i cc [ma] f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz ? 50 0 + 50 + 100 + 150 t a [ c] 0 1 3 2 4 1234567 i ccs [ma] v cc [v] f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz 0 1 2 4 3 i ccs [ma] f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz ? 50 0 + 50 + 100 + 150 t a [ c] 0 20 60 40 140 120 100 80 1234567 i ccl [ a] v cc [v] 0 20 40 140 120 100 80 60 i ccl [ a] ? 50 0 + 50 + 100 + 150 t a [ c] i cc ? t a v cc ? 3.3v, f mp ? 2, 4, 8, 10, 16 mhz (divided by 2) main clock mode with the external clock operating i ccs ? v cc t a ? ? 25 ? c, f mp ? 2, 4, 8, 10, 16 mhz (divided by 2) main sleep mode with the external clock operating i ccs ? t a v cc ? 3.3 v, f mp ? 2, 4, 8, 10, 16 mhz (divided by 2) main sleep mode with the external clock operating i ccl ? v cc t a ? ? 25 ? c, f mpl ? 16 khz (divided by 2) subclock mode with the external clock operating i ccl ? t a v cc ? 3.3 v, f mpl ? 16 khz (divided by 2) subclock mode with the external clock operating
document number: 002-04696 rev. *a page 92 of 105 mb95650l series 0 1 2 5 4 3 i cct [ a] ? 50 0 + 50 + 100 + 150 t a [ c] i cct ? t a v cc ? 3.3 v, f mpl ? 16 khz (divided by 2) watch mode with the external clock operating 0 2 5 10 9 8 7 6 1 3 4 i ccls [ a] ? 50 0 + 50 + 100 + 150 t a [ c] i ccls ? t a v cc ? 3.3 v, f mpl ? 16 khz (divided by 2) subsleep mode with the external clock operating 0 2 1 5 4 3 10 9 8 7 6 1234567 i ccls [ a] v cc [v] 0 1 3 2 5 4 1234567 i cct [ a] v cc [v] 0 200 100 400 300 600 500 1234567 i ccts [ a] v cc [v] f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz 0 100 300 200 600 500 400 i ccts [ a] f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz ? 50 0 + 50 + 100 + 150 t a [ c] i ccls ? v cc t a ? ? 25 ? c, f mpl ? 16 khz (divided by 2) subsleep mode with the external clock operating i cct ? v cc t a ? ? 25 ? c, f mpl ? 16 khz (divided by 2) watch mode with the external clock operating i ccts ? v cc t a ? ? 25 ? c, f mp ? 2, 4, 8, 10, 16 mhz (divided by 2) time-base timer mode with the external clock operating i ccts ? t a v cc ? 3.3 v, f mp ? 2, 4, 8, 10, 16 mhz (divided by 2) time-base timer mode with the external clock operating
document number: 002-04696 rev. *a page 93 of 105 mb95650l series (continued) 0 1 2 5 4 3 i cch [ a] ? 50 0 + 50 + 100 + 150 t a [ c] i cch ? t a v cc ? 3.3 v, f mpl ? (stop) substop mode with the ex ternal clock stopping 0 1 3 2 5 4 1234567 i cch [ a] v cc [v] 0 1 3 2 5 4 1234567 i ccmcr [ma] v cc [v] 0 1 2 5 4 3 i ccmcr [ma] ? 50 0 + 50 + 100 + 150 t a [ c] 0 2 6 4 10 8 1234567 i ccmcrpll [ma] v cc [v] 0 2 4 10 8 6 i ccmcrpll [ma] ? 50 0 + 50 + 100 + 150 t a [ c] i cch ? v cc t a ? ? 25 ? c, f mpl ? (stop) substop mode with the external clock stopping i ccmcr ? v cc t a ? ? 25 ? c, f mp ? 4 mhz (no division) main cr clock mode i ccmcr ? t a v cc ? 3.3 v, f mp ? 4 mhz (no division) main cr clock mode i ccmcrpll ? v cc t a ? ? 25 ? c, f mp ? 16 mhz (pll multiplication rate: 4) main cr pll clock mode i ccmcrpll ? t a v cc ? 3.3 v, f mp ? 16 mhz (pll multiplication rate: 4) main cr pll clock mode
document number: 002-04696 rev. *a page 94 of 105 mb95650l series (continued) 0 50 200 150 100 i ccscr [ a] ? 50 0 + 50 + 100 + 150 t a [ c] i ccscr ? t a v cc ? 3.3 v, f mpl ? 50 khz (divided by 2) sub-cr clock mode 0 100 50 200 150 1234567 i ccscr [ a] v cc [v] i ccscr ? v cc t a ? ? 25 ? c, f mpl ? 50 khz (divided by 2) sub-cr clock mode 0 2 6 4 10 8 1234567 i ccmpll [ma] v cc [v] 0 2 4 10 8 6 i ccmpll [ma] ? 50 0 + 50 + 100 + 150 t a [ c] i ccmpll ? v cc t a ? ? 25 ? c, f mp ? 16 mhz (pll multiplication rate: 4) main pll clock mode i ccmpll ? t a v cc ? 3.3 v, f mp ? 16 mhz (pll multiplication rate: 4) main pll clock mode
document number: 002-04696 rev. *a page 95 of 105 mb95650l series input voltage characteristics 0 1 2 4 5 1 3456 2 v ihi1 /v ili [v] v cc [v] 3 v ihi1 v ili 0 1 2 4 5 1 3456 2 v ihi2 /v ili [v] v cc [v] 3 v ihi2 v ili v ihi1 ? v cc and v ili ? v cc t a ? ? 25 ? c v ihi2 ? v cc and v ili ? v cc t a ? ? 25 ? c 0 1 2 4 5 1 3456 2 v ihs /v ils [v] v cc [v] 3 v ihs v ils 0 1 2 4 5 1 3456 2 v ihm /v ilm [v] v cc [v] 3 v ihm v ilm v ihs ? v cc and v ils ? v cc t a ? ? 25 ? c v ihm ? v cc and v ilm ? v cc t a ? ? 25 ? c
document number: 002-04696 rev. *a page 96 of 105 mb95650l series output voltage characteristics 0.0 0.2 0.4 0.8 1.0 0 ? 2 ? 1 ? 3 ? 5 ? 7 ? 9 ? 4 ? 6 ? 8 ? 10 ? 11 ? 12 ? 13 ? 14 ? 15 v cc ? v oh2 [v] i oh [ma] 0.6 v cc = 2.0 v v cc = 2.4 v v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v v cc = 4.0 v v cc = 1.8 v v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v (v cc ? v oh2 ) ? i oh t a ? ? 25 ? c v ol1 ? i ol t a ? ? 25 ? c 0.0 0.2 0.4 0.8 1.0 0 ? 2 ? 1 ? 3 ? 5 ? 7 ? 9 ? 4 ? 6 ? 8 ? 10 ? 11 ? 12 ? 13 ? 14 ? 15 v cc ? v oh1 [v] i oh [ma] 0.6 v cc = 2.0 v v cc = 2.4 v v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v v cc = 4.0 v v cc = 1.8 v v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v (v cc ? v oh1 ) ? i oh t a ? ? 25 ? c 0.0 0.2 0.4 0.8 1.0 02 13579 4 6 8 101112131415 v ol2 [v] i ol [ma] 0.6 v cc = 2.0 v v cc = 2.4 v v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v v cc = 4.0 v v cc = 1.8 v v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v v ol2 ? i ol t a ? ? 25 ? c 0.0 0.2 0.4 0.8 1.0 02 13579 4 6 8 101112131415 v ol1 [v] i ol [ma] 0.6 v cc = 2.0 v v cc = 2.4 v v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v v cc = 4.0 v v cc = 1.8 v v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v
document number: 002-04696 rev. *a page 97 of 105 mb95650l series pull-up characteristics 0 50 100 150 300 250 200 2 1 3456 r pull [k ] v cc [v] r pull ? v cc t a ? ? 25 ? c
document number: 002-04696 rev. *a page 98 of 105 mb95650l series 20. mask options no. part number mb95f652e mb95f653e mb95f654e mb95f656e mb95f652l mb95f653l mb95f654l mb95f656l selectable/fixed fixed 1 low-voltage detection reset/interrupt with low-voltage detection reset/interrupt without low-voltage detection reset/interrupt 2 reset without dedicated reset input with dedicated reset input
document number: 002-04696 rev. *a page 99 of 105 mb95650l series 21. ordering information part number package mb95f652epft-g-sne2 mb95f652lpft-g-sne2 mb95f653epft-g-sne2 mb95f653lpft-g-sne2 mb95f654epft-g-sne2 mb95f654lpft-g-sne2 mb95f656epft-g-sne2 mb95f656lpft-g-sne2 24-pin plastic tssop (FPT-24P-M10) mb95f652epf-g-sne2 mb95f652lpf-g-sne2 mb95f653epf-g-sne2 mb95f653lpf-g-sne2 mb95f654epf-g-sne2 mb95f654lpf-g-sne2 mb95f656epf-g-sne2 mb95f656lpf-g-sne2 24-pin plastic sop (fpt-24p-m34) mb95f652ewqn-g-sne1 mb95f652ewqn-g-snere1 mb95f652lwqn-g-sne1 mb95f652lwqn-g-snere1 mb95f653ewqn-g-sne1 mb95f653ewqn-g-snere1 mb95f653lwqn-g-sne1 mb95f653lwqn-g-snere1 mb95f654ewqn-g-sne1 mb95f654ewqn-g-snere1 mb95f654lwqn-g-sne1 mb95f654lwqn-g-snere1 mb95f656ewqn-g-sne1 mb95f656ewqn-g-snere1 mb95f656lwqn-g-sne1 mb95f656lwqn-g-snere1 32-pin plastic qfn (lcc-32p-m19)
document number: 002-04696 rev. *a page 100 of 105 mb95650l series 22. package dimension (continued) 24-pin plastic tssop lead pitch 0.65 mm package width package length 4.40 mm 7.80 mm lead shape gullwing sealing method plastic mold mounting height 1.20 mm max weight 0.10 g 24-pin plastic tssop (FPT-24P-M10) (FPT-24P-M10) c 2008-2010 fujitsu semiconductor limited f24033s-c-1-2 7.800.10(.307.004) 0.65(.026) (.173.004) 4.400.10 6.400.20 (.252.008) 0.10(.004) "a" index # # btm e-mark 1 12 24 13 0.22 .008 0.10(.004) .005 0.13 1.20(.047) (.004.002) 0.600.15 (.024.006) 0~8 details of "a" part (stand off) (mounting height) 0.100.05 max +0.07 +.003 ?0.02 ?.001 +0.06 +.002 ?0.03 ?.001 dimensions in mm (inches). note: the values in parentheses are reference values. note 1) pins width and pins thickness include plating thickness. note 2) pins width do not include tie bar cutting remainder. note 3) #: these dimensions do not include resin protrusion.
document number: 002-04696 rev. *a page 101 of 105 mb95650l series (continued) 24-pin plastic sop lead pitch 1.27 mm package width package length 7.50 mm 15.34 mm lead shape gullwing lead bend direction normal bend sealing method plastic mold mounting height 2.80 mm max weight 0.44 g 24-pin plastic sop (fpt-24p-m34) (fpt-24p-m34) c 2009-2010 fujitsu semiconductor limited f24034s-c-1-2 0.25(.010) m details of "a" part *15.34 0.10(.604 .004) index 1.27(.050) 0.10(.004) 0.42 0.07 (.017 .003) 0.27 0.07 (.011 .003) "a" 0.25(.010) 1 12 13 24 7.50 0.10 10.20 0.40 (.402 .016) (.295 .004) 2.60 0.15 .006 0.60 0.20 (.024 .008) ?1.20 0.1 dep0.20 ?.047 .004 dep.008 .102 ? .010 +.008 0~8 ? 0.25 +0.20 ? .002 +.004 ? 0.05 +0.10 ? .004 +.006 ? 0.10 +0.15 dimensions in mm (inches). note: the values in parentheses are reference values. note 1) * : these dimensions do not include resin protrusion.
document number: 002-04696 rev. *a page 102 of 105 mb95650l series (continued) 32-pin plastic qfn lead pitch 0.50 mm package width package length 5.00 mm 5.00 mm sealing method plastic mold mounting height 0.80 mm max weight 0.06 g 32-pin plastic qfn (lcc-32p-m19) (lcc-32p-m19) (.010 ) c 2009-2010 fujitsu semiconductor limited c32071s-c-1-2 (.197 .004) 5.00 0.10 5.00 0.10 (.197 .004) (3-r0.20) ((3-r.008)) 0.50(.020) 1pin corner (c0.30(c.012)) 0.75 0.05 (0.20(.008)) index area 0.40 0.05 (.016 .002) +0.03 ? 0.02 ? .001 +.001 0.02 (.001 ) (.138 .004) 3.50 0.10 3.50 0.10 (.138 .004) (typ) (.030 .002) +0.05 ? 0.07 ? .003 +.002 0.25 dimensions in mm (inches). note: the values in parentheses are reference values.
document number: 002-04696 rev. *a page 103 of 105 mb95650l series 23. major changes spansion publication number: ds702?00016?3v0-e note: please see ?document history? about later revised information. page section details 19 pin connection ?c pin corrected the following statement. the bypass capacitor for the v cc pin must have a capacitance larger than c s . ? the decoupling capacitor for the v cc pin must have a capacitance equal to or larger than the capacitance of c s . 64 electrical characteristics 4. ac characteristics (1) clock timing corrected the pin name of the parameter ?input clock rising time and falling time?. x0 ? x0, x0a
document number: 002-04696 rev. *a page 104 of 105 mb95650l series document history document title: mb95650l series new 8fx 8-bit microcontrollers document number: 002-04696 revision ecn orig. of change submission date description of change ** ? akih 06/14/2013 migrated to cypress and assigned document number 002-04696. no change to document contents or format. *a 5216808 akih 04/12/2016 updated to cypress format.
document number: 002-04696 rev. *a revised april 12, 2016 page 105 of 105 mb95650l series ? cypress semiconductor corporation, 2012-2016. this document is the property of cypress semiconductor corporation and its subs idiaries, including spansion llc ("cypress"). this document, including any software or firmware included or referenced in this document ("software"), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragr aph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a writte n agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units, and (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware product s. any other use, reproduction, modification, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this docum ent or any software or accompanying hardware, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. any information provided in this document, including any sample design informat ion or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly desi gn, program, and test the functionality and safety of any appli cation made of this information and any resulting product. cypress products are not designed, intended, or authorized fo r use as critical components in systems de signed or intended for the operation of w eapons, weapons systems, nuclear inst allations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("unintended uses"). a crit ical component is any compo nent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. cypress is not liable, in who le or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unintended uses of cypress products. you shall indemnify and hold cy press harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inju ry or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, psoc, capsense, ez-usb, f-ram, and traveo are trademarks or registered trad emarks of cypress in the united states and other countries. for a more complete list of cypre ss trademarks, visit cypress.com. other names and brands may be claimed as property of their respective owners. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface lighting & power control cypress.com/powerpsoc memory cypress.com/memory psoc cypress.com/psoc touch sensing cypress.com/touch usb controllers cypress.com/usb wireless/rf cypress.com/wireless psoc ? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community forums | projects | video | blogs | training | components technical support cypress.com/support

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